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Evaluating Soft Core RISC-V Processor in SRAM-Based FPGA Under Radiation Effects

IEEE transactions on nuclear science, 2020-07, Vol.67 (7), p.1503-1510

2020

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Register File Criticality and Compiler Optimization Effects on Embedded Microprocessor Reliability

IEEE transactions on nuclear science, 2017-08, Vol.64 (8), p.2179-2187

2017

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S-SETA: Selective Software-Only Error-Detection Technique Using Assertions

IEEE transactions on nuclear science, 2015-12, Vol.62 (6), p.3088-3095

2015

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Single Event Transients in Logic Circuits-Load and Propagation Induced Pulse Broadening

IEEE transactions on nuclear science, 2008-12, Vol.55 (6), p.2928-2935

2008

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Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques

IEEE transactions on nuclear science, 2016-08, Vol.63 (4), p.2208-2216

2016

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Failure Mechanism and Sampling Frequency Dependency on TID Response of SAR ADCs

Journal of electronic testing, 2021-06, Vol.37 (3), p.329-343

2021

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Reducing Soft Error Rate of SoCs Analog-to-Digital Interfaces With Design Diversity Redundancy

IEEE transactions on nuclear science, 2020-03, Vol.67 (3), p.518-524

2020

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Circuit design using Schmitt Trigger to reliability improvement

Microelectronics and reliability, 2020-11, Vol.114, p.113754, Article 113754

2020

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Reliability Calculation With Respect to Functional Failures Induced by Radiation in TMR Arm Cortex-M0 Soft-Core Embedded Into SRAM-Based FPGA

IEEE transactions on nuclear science, 2019-07, Vol.66 (7), p.1433-1440

2019

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Exploring Gate Mapping and Transistor Sizing to Improve Radiation Robustness: A C17 Benchmark Case-study

2021 IEEE 22nd Latin American Test Symposium (LATS), 2021, p.1-6

2021

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Circuit-Level Techniques to Mitigate Process Variability and Soft Errors in FinFET Designs

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, p.240-241

2019

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Hybrid soft error mitigation techniques for COTS processor-based systems

2016 17th Latin-American Test Symposium (LATS), 2016, p.99-104

2016

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Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects

Applied Reconfigurable Computing, p.331-338

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Using majority logic to cope with long duration transient faults

Proceedings of the 20th annual conference on integrated circuits and systems design, 2007, p.354-359

2007

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Approximate Computing for Fault Tolerance Mechanisms for Safety-Critical Applications

Approximate Computing Techniques, p.387-414

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Register file criticality on embedded microprocessor reliability

2016 16th European Conference on Radiation and Its Effects on Components and Systems (RADECS), 2016, p.1-5

2016

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Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs

2007 IEEE International Symposium on Circuits and Systems (ISCAS), 2007, p.3776-3779

2007

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Analyzing the impact of using pthreads versus OpenMP under fault injection in ARM Cortex-A9 dual-core

2016 16th European Conference on Radiation and Its Effects on Components and Systems (RADECS), 2016, p.1-6

2016

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Volltext

Investigating parallel TMR approaches and thread disposability in Linux

2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2017, p.393-396

2017

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Simulation of SET faults in a voltage controlled oscillator

2012 13th Latin American Test Workshop (LATW), 2012, p.1-6

2012

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Evaluating the effectiveness of a diversity TMR scheme under neutrons

2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS), 2013, p.1-5

2013

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Volltext

Improving error detection with selective redundancy in software-based techniques

2013 14th Latin American Test Workshop - LATW, 2013, p.1-6

2013

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Fault-Tolerant Manager Core for Dynamic Partial Reconfiguration in FPGAs

FPGAs and Parallel Architectures for Aerospace Applications, p.121-133

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Reducing TMR overhead by combining approximate circuit, transistor topology and input permutation approaches

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), 2013, p.1-6

2013

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Soft error rate in SRAM-based FPGAs under neutron-induced and TID effects

2014 15th Latin American Test Workshop - LATW, 2014, p.1-6

2014

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Evaluating Soft Core RISC-V Processor in SRAM-Based FPGA Under Radiation Effects

Register File Criticality and Compiler Optimization Effects on Embedded Microprocessor Reliability

S-SETA: Selective Software-Only Error-Detection Technique Using Assertions

Single Event Transients in Logic Circuits-Load and Propagation Induced Pulse Broadening

Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques

Failure Mechanism and Sampling Frequency Dependency on TID Response of SAR ADCs

Reducing Soft Error Rate of SoCs Analog-to-Digital Interfaces With Design Diversity Redundancy

Circuit design using Schmitt Trigger to reliability improvement

Reliability Calculation With Respect to Functional Failures Induced by Radiation in TMR Arm Cortex-M0 Soft-Core Embedded Into SRAM-Based FPGA

Exploring Gate Mapping and Transistor Sizing to Improve Radiation Robustness: A C17 Benchmark Case-study

Circuit-Level Techniques to Mitigate Process Variability and Soft Errors in FinFET Designs

Hybrid soft error mitigation techniques for COTS processor-based systems

Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects

Using majority logic to cope with long duration transient faults

Approximate Computing for Fault Tolerance Mechanisms for Safety-Critical Applications

Register file criticality on embedded microprocessor reliability

Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs

Analyzing the impact of using pthreads versus OpenMP under fault injection in ARM Cortex-A9 dual-core

Investigating parallel TMR approaches and thread disposability in Linux

Simulation of SET faults in a voltage controlled oscillator

Evaluating the effectiveness of a diversity TMR scheme under neutrons

Improving error detection with selective redundancy in software-based techniques

Fault-Tolerant Manager Core for Dynamic Partial Reconfiguration in FPGAs

Reducing TMR overhead by combining approximate circuit, transistor topology and input permutation approaches

Soft error rate in SRAM-based FPGAs under neutron-induced and TID effects

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