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Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors

IEEE journal of solid-state circuits, 2020-01, Vol.55 (1), p.203-215

2020

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Security and Privacy of Blockchain-Based Single-Bit Cache Memory Architecture for IoT Systems

IEEE access, 2022, Vol.10, p.35273-35286

2022

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Analysis and Design of Reconfigurable Sense Amplifier for Compute SRAM With High-Speed Compute and Normal Read Access

IEEE transactions on circuits and systems. II, Express briefs, 2021-12, Vol.68 (12), p.3503-3507

2021

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A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination

IEEE journal of solid-state circuits, 2019-01, Vol.54 (1), p.231-239

2019

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A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference

IEEE journal of solid-state circuits, 2023-10, Vol.58 (10), p.1-12

2023

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Reimagining Sense Amplifiers: Harnessing Phase Transition Materials for Current and Voltage Sensing

IEEE transactions on nanotechnology, 2024, Vol.23, p.606-614

2024

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Yield and speed optimization of a latch-type voltage sense amplifier

IEEE journal of solid-state circuits, 2004-07, Vol.39 (7), p.1148-1158

2004

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An Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Boosted Internal-Voltage-Difference

IEEE transactions on circuits and systems. II, Express briefs, 2023-09, Vol.70 (9), p.3243-3247

2023

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Multi-Logic Sense Amplifier (MLSA) Design for In-Memory Computing

IEEE journal on emerging and selected topics in circuits and systems, 2023-03, Vol.13 (1), p.1-1

2023

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5.6 Mb/mm ^ 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology

IEEE journal of solid-state circuits, 2017-01, Vol.52 (1), p.229-239

2017

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Flip Point Offset-Compensation Sense Amplifier With Sensing-Margin-Enhancement for Dynamic Random-Access Memory

IEEE transactions on circuits and systems. II, Express briefs, 2024-04, Vol.71 (4), p.1759-1763

2024

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A 9-Mb HZO-Based Embedded FeRAM With 10-Cycle Endurance and 5/7-ns Read/Write Using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier

IEEE journal of solid-state circuits, 2024-01, Vol.59 (1), p.208-218

2024

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A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory

IEEE transactions on circuits and systems. II, Express briefs, 2023-10, Vol.70 (10), p.1-1

2023

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A 28-nm 320-Kb TCAM Macro Using Split-Controlled Single-Load 14T Cell and Triple-Margin Voltage Sense Amplifier

IEEE journal of solid-state circuits, 2019-10, Vol.54 (10), p.2743-2753

2019

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Cross-Coupled nFET Preamplifier for Low Voltage SRAM

IEEE transactions on circuits and systems. II, Express briefs, 2023-09, Vol.70 (9), p.3604-3608

2023

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A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Reduced Variation of Decision Threshold Voltage

IEEE journal of solid-state circuits, 2020-08, Vol.55 (8), p.2219-2227

2020

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Timing Optimization Model and PVT Tracked Scheme for STT-MRAM Voltage-Mode Sense

IEEE transactions on circuits and systems. I, Regular papers, 2024-09, Vol.71 (9), p.4019-4031

2024

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Fast and Efficient Offset Compensation by Noise-Aware Pre-Charge and Operation of DRAM Bit Line Sense Amplifier

IEEE transactions on circuits and systems. II, Express briefs, 2023-04, Vol.70 (4), p.1326-1330

2023

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Novel Radiation Hardened Pre-Discharge Sense Amplifier for Double Data Rate Magnetic Random Access Memory

IEEE transactions on circuits and systems. I, Regular papers, 2024-07, Vol.71 (7), p.3179-3188

2024

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A Single-Ended Offset-Canceling Sense Amplifier Enabling Wide-Voltage Operations

IEEE transactions on circuits and systems. II, Express briefs, 2023-03, Vol.70 (3), p.1-1

2023

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Offset-Compensation High-Performance Sense Amplifier for Low-Voltage DRAM Based on Current Mirror and Switching Point

IEEE transactions on circuits and systems. II, Express briefs, 2022-04, Vol.69 (4), p.2011-2015

2022

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Efficient replica bitline technique for variation-tolerant timing generation scheme of SRAM sense amplifiers

Electronics letters, 2015-05, Vol.51 (10), p.742-743

2015

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Ferroelectric FET Nonvolatile Sense-Amplifier-Based Flip-Flops for Low Voltage Operation

IEEE transactions on circuits and systems. I, Regular papers, 2024-01, Vol.71 (1), p.1-13

2024

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Analysis of SRAM Enhancements Through Sense Amplifier Capacitive Offset Correction and Replica Self-Timing

IEEE transactions on circuits and systems. I, Regular papers, 2019-06, Vol.66 (6), p.2037-2050

2019

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Single-ended structure sense-amplifier-based flip-flop for low-power systems

Electronics letters, 2015-01, Vol.51 (1), p.20-21

2015

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Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors

Security and Privacy of Blockchain-Based Single-Bit Cache Memory Architecture for IoT Systems

Analysis and Design of Reconfigurable Sense Amplifier for Compute SRAM With High-Speed Compute and Normal Read Access

A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination

A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference

Reimagining Sense Amplifiers: Harnessing Phase Transition Materials for Current and Voltage Sensing

Yield and speed optimization of a latch-type voltage sense amplifier

An Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Boosted Internal-Voltage-Difference

Multi-Logic Sense Amplifier (MLSA) Design for In-Memory Computing

5.6 Mb/mm ^ 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology

Flip Point Offset-Compensation Sense Amplifier With Sensing-Margin-Enhancement for Dynamic Random-Access Memory

A 9-Mb HZO-Based Embedded FeRAM With 10-Cycle Endurance and 5/7-ns Read/Write Using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier

A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory

A 28-nm 320-Kb TCAM Macro Using Split-Controlled Single-Load 14T Cell and Triple-Margin Voltage Sense Amplifier

Cross-Coupled nFET Preamplifier for Low Voltage SRAM

A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Reduced Variation of Decision Threshold Voltage

Timing Optimization Model and PVT Tracked Scheme for STT-MRAM Voltage-Mode Sense

Fast and Efficient Offset Compensation by Noise-Aware Pre-Charge and Operation of DRAM Bit Line Sense Amplifier

Novel Radiation Hardened Pre-Discharge Sense Amplifier for Double Data Rate Magnetic Random Access Memory

A Single-Ended Offset-Canceling Sense Amplifier Enabling Wide-Voltage Operations

Offset-Compensation High-Performance Sense Amplifier for Low-Voltage DRAM Based on Current Mirror and Switching Point

Efficient replica bitline technique for variation-tolerant timing generation scheme of SRAM sense amplifiers

Ferroelectric FET Nonvolatile Sense-Amplifier-Based Flip-Flops for Low Voltage Operation

Analysis of SRAM Enhancements Through Sense Amplifier Capacitive Offset Correction and Replica Self-Timing

Single-ended structure sense-amplifier-based flip-flop for low-power systems

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