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Analysis of frequency detection capability of Alexander phase detector

Electronics letters, 2020-02, Vol.56 (4), p.180-182

2020

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Synthesisable glitch-less phase rotator with conditionally cascading scheme

Electronics letters, 2020-05, Vol.56 (11), p.536-538

2020

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A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS

IEEE journal of solid-state circuits, 2016-10, Vol.51 (10), p.2357-2367

2016

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Ultra-low-voltage low-power dynamic comparator with forward body bias scheme for SAR ADC

Electronics letters, 2018-11, Vol.54 (24), p.1370-1372

2018

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An AC–DC LED Driver With a Two-Parallel Inverted Buck Topology for Reducing the Light Flicker in Lighting Applications to Low-Risk Levels

IEEE transactions on power electronics, 2017-05, Vol.32 (5), p.3879-3891

2017

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A Reconfigurable 40-to-67 dB SNR, 50-to-6400 Hz Frame-Rate, Column-Parallel Readout IC for Capacitive Touch-Screen Panels

IEEE journal of solid-state circuits, 2014-10, Vol.49 (10), p.2305-2318

2014

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Balancing scheme for phase current and flying-capacitor voltage in three-level DC–DC converter

Electronics letters, 2020-04, Vol.56 (9), p.426-428

2020

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A Fully Passive Noise-Shaping SAR ADC Utilizing Last-Bit Majority Voting and Cyclic Dynamic Element Matching Techniques

IEEE transactions on very large scale integration (VLSI) systems, 2022-10, Vol.30 (10), p.1381-1390

2022

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A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards

IEEE transactions on industrial electronics (1982), 2018-07, Vol.65 (7), p.5979-5989

2018

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Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection

Sensors (Basel, Switzerland), 2017-08, Vol.17 (9), p.1962

2017

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A 0.4-to-1 V Voltage Scalable \Delta \Sigma ADC With Two-Step Hybrid Integrator for IoT Sensor Applications in 65-nm LP CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2017-12, Vol.64 (12), p.1417-1421

2017

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A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process

IEEE journal of solid-state circuits, 2015-11, Vol.50 (11), p.2603-2612

2015

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A Practical Implementation of IEEE 1588-2008 Transparent Clock for Distributed Measurement and Control Systems

IEEE transactions on instrumentation and measurement, 2010-02, Vol.59 (2), p.433-439

2010

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A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver With Dead-Zone Free SS-MMSE PD for CIS Link

IEEE access, 2023, Vol.11, p.46513-46521

2023

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A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection

IEEE transactions on circuits and systems. I, Regular papers, 2018-09, Vol.65 (9), p.2691-2702

2018

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Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator

IEEE journal of solid-state circuits, 2014-03, Vol.49 (3), p.657-672

2014

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Extension of Two-Port Sneak Current Cancellation Scheme to 3-D Vertical RRAM Crossbar Array

IEEE transactions on electron devices, 2017-04, Vol.64 (4), p.1591-1596

2017

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Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis

IEEE transactions on very large scale integration (VLSI) systems, 2017-12, Vol.25 (12), p.3543-3547

2017

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A 28 Gb/s Receiver Front-end Capable of Receiving Wide Range Current Signal in 65 nm CMOS

Journal of semiconductor technology and science, 2022-12, Vol.22 (6), p.475-481

2022

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Design of Soft-Switching Hybrid DC-DC Converter with 2-Phase Switched Capacitor and 0.8nH Inductor for Standard CMOS Process

Electronics (Basel), 2020-02, Vol.9 (2), p.372

2020

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An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection

IEEE transactions on circuits and systems. II, Express briefs, 2015-09, Vol.62 (9), p.836-840

2015

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Comprehensive Writing Margin Analysis and its Application to Stacked one Diode-One Memory Device for High-Density Crossbar Resistance Switching Random Access Memory

Advanced electronic materials, 2016-10, Vol.2 (10), p.n/a

2016

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A 0.015-mm ^} Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology

IEEE transactions on circuits and systems. II, Express briefs, 2017-06, Vol.64 (6), p.655-659

2017

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A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors

IEEE access, 2019, Vol.7, p.63686-63697

2019

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A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference

IEEE journal of solid-state circuits, 2020-08, Vol.55 (8), p.2186-2195

2020

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Analysis of frequency detection capability of Alexander phase detector

Synthesisable glitch-less phase rotator with conditionally cascading scheme

A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS

Ultra-low-voltage low-power dynamic comparator with forward body bias scheme for SAR ADC

An AC–DC LED Driver With a Two-Parallel Inverted Buck Topology for Reducing the Light Flicker in Lighting Applications to Low-Risk Levels

A Reconfigurable 40-to-67 dB SNR, 50-to-6400 Hz Frame-Rate, Column-Parallel Readout IC for Capacitive Touch-Screen Panels

Balancing scheme for phase current and flying-capacitor voltage in three-level DC–DC converter

A Fully Passive Noise-Shaping SAR ADC Utilizing Last-Bit Majority Voting and Cyclic Dynamic Element Matching Techniques

A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection

A 0.4-to-1 V Voltage Scalable \Delta \Sigma ADC With Two-Step Hybrid Integrator for IoT Sensor Applications in 65-nm LP CMOS

A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process

A Practical Implementation of IEEE 1588-2008 Transparent Clock for Distributed Measurement and Control Systems

A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver With Dead-Zone Free SS-MMSE PD for CIS Link

A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection

Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator

Extension of Two-Port Sneak Current Cancellation Scheme to 3-D Vertical RRAM Crossbar Array

Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis

A 28 Gb/s Receiver Front-end Capable of Receiving Wide Range Current Signal in 65 nm CMOS

Design of Soft-Switching Hybrid DC-DC Converter with 2-Phase Switched Capacitor and 0.8nH Inductor for Standard CMOS Process

An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection

Comprehensive Writing Margin Analysis and its Application to Stacked one Diode-One Memory Device for High-Density Crossbar Resistance Switching Random Access Memory

A 0.015-mm ^} Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology

A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors

A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference

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