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A 6-to-7.5-GHz 54-fsrms Jitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction

IEEE transactions on circuits and systems. I, Regular papers, 2022-12, Vol.69 (12), p.4774-4786

2022

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Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector

IEEE journal of solid-state circuits, 2022-10, Vol.57 (10), p.3014-3024

2022

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A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS

IEEE journal of solid-state circuits, 2023-05, Vol.58 (5), p.1414-1424

2023

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Analysis of Stochastic Phase-Frequency Detector in 2x Oversampling Clock and Data Recovery

IEEE transactions on circuits and systems. II, Express briefs, 2024-04, Vol.71 (4), p.1844-1848

2024

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A Low-Jitter and Low-Reference-Spur 320 GHz Signal Source With an 80 GHz Integer-N Phase-Locked Loop Using a Quadrature XOR Technique

IEEE transactions on microwave theory and techniques, 2022-05, Vol.70 (5), p.2642-2657

2022

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Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector

IEEE journal of solid-state circuits, 2010-09, Vol.45 (9), p.1809-1821

2010

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A 25.8-GHz Integer-N CPPLL Achieving 60-fs rms Jitter and Robust Lock Acquisition Based on a Time-Amplifying Phase-Frequency Detector

IEEE transactions on microwave theory and techniques, 2023-11, Vol.71 (11), p.1-13

2023

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A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO

IEEE journal of solid-state circuits, 2021-12, Vol.56 (12), p.3756-3767

2021

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A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector

IEEE transactions on very large scale integration (VLSI) systems, 2024-04, Vol.32 (4), p.704-713

2024

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A 2.4-GHz Reference-Sampling Phase-Locked Loop That Simultaneously Achieves Low-Noise and Low-Spur Performance

IEEE journal of solid-state circuits, 2019-05, Vol.54 (5), p.1407-1424

2019

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A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter

IEEE journal of solid-state circuits, 2022-02, Vol.57 (2), p.505-517

2022

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High‐Precision Carrier Tracking Algorithm for Extremely Weak and High‐Dynamic Signals

Radio science, 2021-05, Vol.56 (5), p.n/a

2021

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A Low-Jitter and Low-Spur Charge-Sampling PLL

IEEE journal of solid-state circuits, 2022-02, Vol.57 (2), p.492-504

2022

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Feedforward Phase Noise Cancellation Exploiting a Sub-Sampling Phase Detector

IEEE transactions on circuits and systems. II, Express briefs, 2018-11, Vol.65 (11), p.1574-1578

2018

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A 40 GHz CMOS PLL With −75-dBc Reference Spur and 121.9-fsrms Jitter Featuring a Quadrature Sampling Phase-Frequency Detector

IEEE transactions on microwave theory and techniques, 2022-04, Vol.70 (4), p.2299-2314

2022

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A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking

IEEE journal of solid-state circuits, 2020-12, Vol.55 (12), p.3349-3361

2020

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A 0.65-V 12-16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and −256.4-dB FoM

IEEE journal of solid-state circuits, 2020-06, Vol.55 (6), p.1665-1683

2020

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A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS

IEEE journal of solid-state circuits, 2018-10, Vol.53 (10), p.2982-2993

2018

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A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N

IEEE journal of solid-state circuits, 2009-12, Vol.44 (12), p.3253-3263

2009

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A Cryo-CMOS PLL for Quantum Computing Applications

IEEE journal of solid-state circuits, 2023-05, Vol.58 (5), p.1-14

2023

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Enhanced Jitter Analysis and Minimization for Digital PLLs With Mid-Rise TDCs and its Impact on Output Phase Noise

IEEE transactions on circuits and systems. I, Regular papers, 2023-12, Vol.70 (12), p.1-14

2023

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Phase Shift and Amplitude Array Measurement System Based on 360° Switched Dual Multiplier Phase Detector

IEEE transactions on instrumentation and measurement, 2021, Vol.70, p.1-11

2021

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A 20-GHz PLL With 20.9-fs Random Jitter

IEEE journal of solid-state circuits, 2023-06, Vol.58 (6), p.1597-1609

2023

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A 0.003-mm2 440fsRMS-Jitter and −64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS

IEEE transactions on circuits and systems. I, Regular papers, 2021-06, Vol.68 (6), p.2307-2316

2021

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A 2.4-GHz 16-Phase Sub-Sampling Fractional-N PLL With Robust Soft Loop Switching

IEEE journal of solid-state circuits, 2018-03, Vol.53 (3), p.715-727

2018

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A 6-to-7.5-GHz 54-fsrms Jitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction

Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector

A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS

Analysis of Stochastic Phase-Frequency Detector in 2x Oversampling Clock and Data Recovery

A Low-Jitter and Low-Reference-Spur 320 GHz Signal Source With an 80 GHz Integer-N Phase-Locked Loop Using a Quadrature XOR Technique

Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector

A 25.8-GHz Integer-N CPPLL Achieving 60-fs rms Jitter and Robust Lock Acquisition Based on a Time-Amplifying Phase-Frequency Detector

A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO

A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector

A 2.4-GHz Reference-Sampling Phase-Locked Loop That Simultaneously Achieves Low-Noise and Low-Spur Performance

A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter

High‐Precision Carrier Tracking Algorithm for Extremely Weak and High‐Dynamic Signals

A Low-Jitter and Low-Spur Charge-Sampling PLL

Feedforward Phase Noise Cancellation Exploiting a Sub-Sampling Phase Detector

A 40 GHz CMOS PLL With −75-dBc Reference Spur and 121.9-fsrms Jitter Featuring a Quadrature Sampling Phase-Frequency Detector

A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking

A 0.65-V 12-16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and −256.4-dB FoM

A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS

A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N

A Cryo-CMOS PLL for Quantum Computing Applications

Enhanced Jitter Analysis and Minimization for Digital PLLs With Mid-Rise TDCs and its Impact on Output Phase Noise

Phase Shift and Amplitude Array Measurement System Based on 360° Switched Dual Multiplier Phase Detector

A 20-GHz PLL With 20.9-fs Random Jitter

A 0.003-mm2 440fsRMS-Jitter and −64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS

A 2.4-GHz 16-Phase Sub-Sampling Fractional-N PLL With Robust Soft Loop Switching

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