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Elementary Aspects for Circuit Implementation of Reconfigurable Nanowire Transistors

IEEE electron device letters, 2014-01, Vol.35 (1), p.141-143

2014

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Three-to-one analog signal modulation with a single back-bias-controlled reconfigurable transistor

Nature communications, 2022-11, Vol.13 (1), p.7042-7042, Article 7042

2022

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Enabling Energy Efficiency and Polarity Control in Germanium Nanowire Transistors by Individually Gated Nanojunctions

ACS nano, 2017-02, Vol.11 (2), p.1704-1711

2017

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Emerging reconfigurable electronic devices based on two‐dimensional materials: A review

InfoMat, 2022-10, Vol.4 (10), p.n/a

2022

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Modulation Doping of Silicon Nanowires to Tune the Contact Properties of Nano‐Scale Schottky Barriers

Advanced materials interfaces, 2024-01, Vol.11 (1), p.n/a

2024

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Generating Predictive Models for Emerging Semiconductor Devices

IEEE journal of the Electron Devices Society, 2024-01, Vol.12, p.1-1

2024

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Physics-Based DC Compact Modeling of Schottky Barrier and Reconfigurable Field-Effect Transistors

IEEE journal of the Electron Devices Society, 2022, Vol.10, p.416-423

2022

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Operation regimes and electrical transport of steep slope Schottky Si-FinFETs

Journal of applied physics, 2017-02, Vol.121 (6)

2017

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Compact FeFET Circuit Building Blocks for Fast and Efficient Nonvolatile Logic-in-Memory

IEEE journal of the Electron Devices Society, 2020, Vol.8, p.748-756

2020

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Silicon nanowires - a versatile technology platform

Physica status solidi. PSS-RRL. Rapid research letters, 2013-10, Vol.7 (10), p.793-799

2013

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Inherent Charge-Sharing-Free Dynamic Logic Gates Employing Transistors With Multiple Independent Inputs

IEEE journal of the Electron Devices Society, 2020, Vol.8, p.740-747

2020

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Quantitative Characterization of Reconfigurable Transistor Logic Gates

IEEE access, 2020, Vol.8, p.112598-112614

2020

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The RGATE: an 8-in-1 Polymorphic Logic Gate Built from Reconfigurable Field Effect Transistors

IEEE electron device letters, 2024-03, p.1-1

2024

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Dopant segregation effects on ohmic contact formation in nanoscale silicon

Solid-state electronics, 2023-10, Vol.208, p.108739, Article 108739

2023

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On Temperature Dependency of Steep Subthreshold Slope in Dual-Independent-Gate FinFET

IEEE journal of the Electron Devices Society, 2015-11, Vol.3 (6), p.452-456

2015

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Insights into the Temperature‐Dependent Switching Behavior of Three‐Gated Reconfigurable Field‐Effect Transistors

Physica status solidi. A, Applications and materials science, 2023-07, Vol.220 (13), p.n/a

2023

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Insights into the Temperature‐Dependent Switching Behavior of Three‐Gated Reconfigurable Field‐Effect Transistors

Physica status solidi. A, Applications and materials science, 2023-07, Vol.220 (13), p.n/a

2023

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Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors

IEEE transactions on very large scale integration (VLSI) systems, 2019-03, Vol.27 (3), p.560-572

2019

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Dually Active Silicon Nanowire Transistors and Circuits with Equal Electron and Hole Transport

Nano letters, 2013-09, Vol.13 (9), p.4176-4181

2013

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On the Operation Modes of Dual-Gate Reconfigurable Nanowire Transistors

IEEE transactions on electron devices, 2021-07, Vol.68 (7), p.3684-3689

2021

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Reconfigurable Field Effect Transistors Design Solutions for Delay-Invariant Logic Gates

IEEE embedded systems letters, 2022-06, Vol.14 (2), p.107-110

2022

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Functionality-Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors

IEEE transactions on nanotechnology, 2015-07, Vol.14 (4), p.689-698

2015

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Corrections to "Pulsed Measurements Based Investigation of Trap Capture and Emission Processes in CNTFETs" [2021 459-465]

IEEE transactions on nanotechnology, 2021, Vol.20, p.561-561

2021

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Robust Reconfigurable Field Effect Transistors Process Route Enabling Multi-VT Devices Fabrication for Hardware Security Applications

2022 Device Research Conference (DRC), 2022, p.1-2

2022

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Top-Down Technology for Reconfigurable Nanowire FETs With Symmetric On-Currents

IEEE transactions on nanotechnology, 2017-09, Vol.16 (5), p.812-819

2017

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Elementary Aspects for Circuit Implementation of Reconfigurable Nanowire Transistors

Three-to-one analog signal modulation with a single back-bias-controlled reconfigurable transistor

Enabling Energy Efficiency and Polarity Control in Germanium Nanowire Transistors by Individually Gated Nanojunctions

Emerging reconfigurable electronic devices based on two‐dimensional materials: A review

Modulation Doping of Silicon Nanowires to Tune the Contact Properties of Nano‐Scale Schottky Barriers

Generating Predictive Models for Emerging Semiconductor Devices

Physics-Based DC Compact Modeling of Schottky Barrier and Reconfigurable Field-Effect Transistors

Operation regimes and electrical transport of steep slope Schottky Si-FinFETs

Compact FeFET Circuit Building Blocks for Fast and Efficient Nonvolatile Logic-in-Memory

Silicon nanowires - a versatile technology platform

Inherent Charge-Sharing-Free Dynamic Logic Gates Employing Transistors With Multiple Independent Inputs

Quantitative Characterization of Reconfigurable Transistor Logic Gates

The RGATE: an 8-in-1 Polymorphic Logic Gate Built from Reconfigurable Field Effect Transistors

Dopant segregation effects on ohmic contact formation in nanoscale silicon

On Temperature Dependency of Steep Subthreshold Slope in Dual-Independent-Gate FinFET

Insights into the Temperature‐Dependent Switching Behavior of Three‐Gated Reconfigurable Field‐Effect Transistors

Insights into the Temperature‐Dependent Switching Behavior of Three‐Gated Reconfigurable Field‐Effect Transistors

Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors

Dually Active Silicon Nanowire Transistors and Circuits with Equal Electron and Hole Transport

On the Operation Modes of Dual-Gate Reconfigurable Nanowire Transistors

Reconfigurable Field Effect Transistors Design Solutions for Delay-Invariant Logic Gates

Functionality-Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors

Corrections to "Pulsed Measurements Based Investigation of Trap Capture and Emission Processes in CNTFETs" [2021 459-465]

Robust Reconfigurable Field Effect Transistors Process Route Enabling Multi-VT Devices Fabrication for Hardware Security Applications

Top-Down Technology for Reconfigurable Nanowire FETs With Symmetric On-Currents

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