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Majority-Inverter Graph: A New Paradigm for Logic Optimization

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-05, Vol.35 (5), p.806-819

2016

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A TCAD Simulation Study of Three-Independent-Gate Field-Effect Transistors at the 10-nm Node

IEEE transactions on electron devices, 2021-08, Vol.68 (8), p.4129-4135

2021

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A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom FPGA Design

IEEE transactions on very large scale integration (VLSI) systems, 2023-08, Vol.31 (8), p.1-12

2023

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A Robust Digital RRAM-Based Convolutional Block for Low-Power Image Processing and Learning Applications

IEEE transactions on circuits and systems. I, Regular papers, 2019-02, Vol.66 (2), p.643-654

2019

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Doping-Free Complementary Logic Gates Enabled by Two-Dimensional Polarity-Controllable Transistors

ACS nano, 2018-07, Vol.12 (7), p.7039-7047

2018

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Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking

IEEE transactions on circuits and systems. I, Regular papers, 2023-05, Vol.70 (5), p.2028-2036

2023

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Programmable Local Clock SET Filtering for SEE-Resistant FPGA

IEEE transactions on circuits and systems. II, Express briefs, 2022-09, Vol.69 (9), p.3879-3883

2022

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FlowTune: End-to-End Automatic Logic Optimization Exploration via Domain-Specific Multiarmed Bandit

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-06, Vol.42 (6), p.1912-1925

2023

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Smart-Redundancy With In Memory ECC Checking: Low-Power SEE-Resistant FPGA Architectures

IEEE transactions on very large scale integration (VLSI) systems, 2023-08, Vol.31 (8), p.1-10

2023

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Exact Synthesis of Majority-Inverter Graphs and Its Applications

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-11, Vol.36 (11), p.1842-1855

2017

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A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.5126-5130

2022

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New Logic Synthesis as Nanotechnology Enabler

Proceedings of the IEEE, 2015-11, Vol.103 (11), p.2168-2195

2015

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A Distributed Low-Cost Pollution Monitoring Platform

IEEE internet of things journal, 2019-12, Vol.6 (6), p.10738-10748

2019

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FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

IEEE transactions on very large scale integration (VLSI) systems, 2019-03, Vol.27 (3), p.637-650

2019

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Configurable Logic Gates Using Polarity-Controlled Silicon Nanowire Gate-All-Around FETs

IEEE electron device letters, 2014-08, Vol.35 (8), p.880-882

2014

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Reconfigurable Logic: Architecture, Tools, and Applications

Gaillardon, Pierre-Emmanuel

1, 2018

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Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction

IEEE transactions on very large scale integration (VLSI) systems, 2023-10, Vol.31 (10), p.1-13

2023

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A Multiply-and-Accumulate Array for Machine Learning Applications Based on a 3D Nanofabric Flow

IEEE transactions on nanotechnology, 2021, Vol.20, p.873-882

2021

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A Resistive Random Access Memory Addon for the NCSU FreePDK 45 nm

IEEE transactions on nanotechnology, 2019, Vol.18, p.68-72

2019

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A Study on the Programming Structures for RRAM-Based FPGA Architectures

IEEE transactions on circuits and systems. I, Regular papers, 2016-04, Vol.63 (4), p.503-516

2016

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Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure

IEEE transactions on circuits and systems. I, Regular papers, 2017-05, Vol.64 (5), p.1173-1186

2017

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A PLiM Computer for the Internet of Things

Computer (Long Beach, Calif.), 2017, Vol.50 (6), p.35-40

2017

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Post-P&R Performance and Power Analysis for RRAM-Based FPGAs

IEEE journal on emerging and selected topics in circuits and systems, 2018-09, Vol.8 (3), p.639-650

2018

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An FPGA-Based Test System for RRAM Technology Characterization

IEEE transactions on nanotechnology, 2018-01, Vol.17 (1), p.177-183

2018

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Guest Editorial Memristive-Device-Based Computing

IEEE transactions on very large scale integration (VLSI) systems, 2018-12, Vol.26 (12), p.2581-2583

2018

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Majority-Inverter Graph: A New Paradigm for Logic Optimization

A TCAD Simulation Study of Three-Independent-Gate Field-Effect Transistors at the 10-nm Node

A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom FPGA Design

A Robust Digital RRAM-Based Convolutional Block for Low-Power Image Processing and Learning Applications

Doping-Free Complementary Logic Gates Enabled by Two-Dimensional Polarity-Controllable Transistors

Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking

Programmable Local Clock SET Filtering for SEE-Resistant FPGA

FlowTune: End-to-End Automatic Logic Optimization Exploration via Domain-Specific Multiarmed Bandit

Smart-Redundancy With In Memory ECC Checking: Low-Power SEE-Resistant FPGA Architectures

Exact Synthesis of Majority-Inverter Graphs and Its Applications

A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal

New Logic Synthesis as Nanotechnology Enabler

A Distributed Low-Cost Pollution Monitoring Platform

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Configurable Logic Gates Using Polarity-Controlled Silicon Nanowire Gate-All-Around FETs

Reconfigurable Logic: Architecture, Tools, and Applications

Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction

A Multiply-and-Accumulate Array for Machine Learning Applications Based on a 3D Nanofabric Flow

A Resistive Random Access Memory Addon for the NCSU FreePDK 45 nm

A Study on the Programming Structures for RRAM-Based FPGA Architectures

Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure

A PLiM Computer for the Internet of Things

Post-P&R Performance and Power Analysis for RRAM-Based FPGAs

An FPGA-Based Test System for RRAM Technology Characterization

Guest Editorial Memristive-Device-Based Computing

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