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TFET Integrated Circuits: From Perspective Towards Reality

1st Edition 2021, 2020

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A Complete Characterization and Modeling of the BTI-Induced Dynamic Variability of SRAM Arrays in 28-nm FD-SOI Technology

IEEE transactions on electron devices, 2014-12, Vol.61 (12), p.3991-3999

2014

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A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm

Journal of low power electronics and applications, 2019, Vol.9 (1), p.8

2019

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Tunnel FET Negative-Differential-Resistance Based 1T1C Refresh-Free-DRAM, 2T1C SRAM and 3T1C CAM

IEEE transactions on nanotechnology, 2021, Vol.20, p.270-277

2021

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CMOS Sensor Nodes With Sub-Picowatt TFET Memory

IEEE sensors journal, 2016-12, Vol.16 (23), p.8255-8262

2016

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SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration

IEEE journal of solid-state circuits, 2023-06, Vol.58 (6), p.1782-1797

2023

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Energy Efficient Comparator-Less Current-Mode TFET-CMOS Co-Integrated Scalable Flash ADC

2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021, p.297-300

2021

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3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, p.361-366

2016

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Tunnel FET based refresh-free-DRAM

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, p.914-917

2017

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Ultra-low leakage SRAM design with sub-32 nm tunnel FETs for low standby power applications

Micro & nano letters, 2016-12, Vol.11 (12), p.828-831

2016

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16Kb hybrid TFET/CMOS reconfigurable CAM/SRAM array based on 9T-TFET bitcell

2016 46th European Solid-State Device Research Conference (ESSDERC), 2016, p.356-359

2016

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Ultra-low leakage sub-32nm TFET/CMOS hybrid 32kb pseudo DualPort scratchpad with GHz speed for embedded applications

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, p.597-600

2015

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Operation and stability analysis of bipolar OxRRAM-based Non-Volatile 8T2R SRAM as solution for information back-up

Solid-state electronics, 2013-12, Vol.90, p.99-106

2013

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Mixed-single well 8T SRAM bitcell for wide voltage range in 28nm FDSOI

2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014, p.1-2

2014

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1.45-fJ/bit Access Two-Port SRAM Interfacing a Synchronous/Asynchronous IoT Platform for Energy-Efficient Normally Off Applications

IEEE solid-state circuits letters, 2018-09, Vol.1 (9), p.186-189

2018

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CMOS SRAM scaling limits under optimum stability constraints

2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, p.1460-1463

2013

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SRAM row decoder design for wide voltage range in 28nm UTBB-FDSOI

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013, p.1-2

2013

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Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization

2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, p.93-98

2012

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Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization

Proceedings of the Conference on Design, Automation and Test in Europe, 2012, p.93-98

2012

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A 32nm tunnel FET SRAM for ultra low leakage

2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012, p.2517-2520

2012

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SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15,000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency

2020 IEEE Symposium on VLSI Circuits, 2020, p.1-2

2020

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Double-Gate Sub-32nm CMOS SRAM current and voltage sense amplifiers, insensitive to process variations and transistor mismatch

2008 IEEE International SOI Conference, 2008, p.63-64

2008

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1.56GHz/0.9V energy-efficient reconfigurable CAM/SRAM using 6T-CMOS bitcell

ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, p.316-319

2017

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An innovative sub-32nm SRAM current sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, 2008, p.47-50

2008

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SRAM voltage and current sense amplifiers in sub-32nm double-gate CMOS insensitive to process variations and transistor mismatch

2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, p.3170-3173

2009

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TFET Integrated Circuits: From Perspective Towards Reality

A Complete Characterization and Modeling of the BTI-Induced Dynamic Variability of SRAM Arrays in 28-nm FD-SOI Technology

A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm

Tunnel FET Negative-Differential-Resistance Based 1T1C Refresh-Free-DRAM, 2T1C SRAM and 3T1C CAM

CMOS Sensor Nodes With Sub-Picowatt TFET Memory

SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration

Energy Efficient Comparator-Less Current-Mode TFET-CMOS Co-Integrated Scalable Flash ADC

3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications

Tunnel FET based refresh-free-DRAM

Ultra-low leakage SRAM design with sub-32 nm tunnel FETs for low standby power applications

16Kb hybrid TFET/CMOS reconfigurable CAM/SRAM array based on 9T-TFET bitcell

Ultra-low leakage sub-32nm TFET/CMOS hybrid 32kb pseudo DualPort scratchpad with GHz speed for embedded applications

Operation and stability analysis of bipolar OxRRAM-based Non-Volatile 8T2R SRAM as solution for information back-up

Mixed-single well 8T SRAM bitcell for wide voltage range in 28nm FDSOI

1.45-fJ/bit Access Two-Port SRAM Interfacing a Synchronous/Asynchronous IoT Platform for Energy-Efficient Normally Off Applications

CMOS SRAM scaling limits under optimum stability constraints

SRAM row decoder design for wide voltage range in 28nm UTBB-FDSOI

Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization

Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization

A 32nm tunnel FET SRAM for ultra low leakage

SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15,000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency

Double-Gate Sub-32nm CMOS SRAM current and voltage sense amplifiers, insensitive to process variations and transistor mismatch

1.56GHz/0.9V energy-efficient reconfigurable CAM/SRAM using 6T-CMOS bitcell

An innovative sub-32nm SRAM current sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch

SRAM voltage and current sense amplifiers in sub-32nm double-gate CMOS insensitive to process variations and transistor mismatch

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