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The Complementary FET (CFET) for CMOS scaling beyond N3

2018 IEEE Symposium on VLSI Technology, 2018, p.141-142

2018

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InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec sub-threshold swing at room temperature

Applied physics letters, 2016-12, Vol.109 (24)

2016

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First Demonstration of Vertically Stacked Gate-All-Around Highly Strained Germanium Nanowire pFETs

IEEE transactions on electron devices, 2018-11, Vol.65 (11), p.5145-5150

2018

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Junctionless versus inversion-mode lateral semiconductor nanowire transistors

Journal of physics. Condensed matter, 2018-09, Vol.30 (38), p.384002-384002

2018

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Epitaxial diamond-hexagonal silicon nano-ribbon growth on (001) silicon

Scientific reports, 2015-08, Vol.5 (1), p.12692-12692, Article 12692

2015

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Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

IEEE transactions on electron devices, 2017-11, Vol.64 (11), p.4587-4593

2017

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Record GmSAT/SSSAT and PBTI Reliability in Si-Passivated Ge nFinFETs by Improved Gate-Stack Surface Preparation

IEEE transactions on electron devices, 2019-12, Vol.66 (12), p.5387-5392

2019

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Electrical Characteristics of p-Type Bulk Si Fin Field-Effect Transistor Using Solid-Source Doping With 1-nm Phosphosilicate Glass

IEEE electron device letters, 2016-09, Vol.37 (9), p.1084-1087

2016

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3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability

IEEE transactions on electron devices, 2018-11, Vol.65 (11), p.5165-5171

2018

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Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

2016 IEEE Symposium on VLSI Technology, 2016, p.1-2

2016

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Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

2015 Symposium on VLSI Technology (VLSI Technology), 2015, p.T56-T57

2015

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Holisitic device exploration for 7nm node

2015 IEEE Custom Integrated Circuits Conference (CICC), 2015, p.1-5

2015

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Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal

2015 Symposium on VLSI Technology (VLSI Technology), 2015, p.T142-T143

2015

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Strained Si CMOS (SS CMOS) technology: opportunities and challenges

Solid-state electronics, 2003-07, Vol.47 (7), p.1133-1139

2003

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Voltage Contrast Inspection Methodology for Inline Detection of Missing Spacer and Other Nonvisual Defects

IEEE transactions on semiconductor manufacturing, 2008-08, Vol.21 (3), p.322-328

2008

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A comparison of arsenic and phosphorus extension by Room Temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7nm) technology relevant fin dimensions

2015 Symposium on VLSI Technology (VLSI Technology), 2015, p.T30-T31

2015

Volltextzugriff (PDF)

New electrical testing structures and analysis method for MOL and BEOL process diagnostics and TDDB reliability assessment

2013 IEEE International Reliability Physics Symposium (IRPS), 2013, p.PI.1.1-PI.1.5

2013

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P80 Two different modalities to end a pregnancy with severe neurological fetal malformations

International journal of gynecology and obstetrics, 2009-10, Vol.107 (S2), p.S434-S434

2009

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Record Gm SAT /SS SAT and PBTI Reliability in Si-Passivated Ge nFinFETs by Improved Gate-Stack Surface Preparation

IEEE transactions on electron devices, 2019-12, Vol.66 (12), p.5387-5392

2019

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Thermal Stability of TiN/Ti/p+-Si0.3Ge0.7 Contact With Ultralow Contact Resistivity

IEEE electron device letters, 2018-01, Vol.39 (1), p.83-86

2018

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Thermal Stability of TiN/Ti/p + -Si 0.3 Ge 0.7 Contact With Ultralow Contact Resistivity

IEEE electron device letters, 2018-01, Vol.39 (1), p.83-86

2018

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Thermal Stability of TiN/Ti/+-Si0.3Ge0.7 Contact With Ultralow Contact Resistivity

IEEE electron device letters, 2018-01, Vol.39 (1), p.83

2018

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Demonstration of 2e12 cm^sup -2^ eV^sup -1^ 2D-oxide interface trap density on back-gated MoS^sub 2^ flake devices with 2.5 nm EOT

Microelectronic engineering, 2017-06, Vol.178, p.145

2017

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Demonstration of 2e12cm−2eV−1 2D-oxide interface trap density on back-gated MoS2 flake devices with 2.5nm EOT

Microelectronic engineering, 2017-06, Vol.178, p.145-149

2017

Volltextzugriff (PDF)

Demonstration of 2e12 cm−2eV−1 2D-oxide interface trap density on back-gated MoS2 flake devices with 2.5 nm EOT

Microelectronic engineering, 2017-06, Vol.178, p.145-149

2017

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The Complementary FET (CFET) for CMOS scaling beyond N3

InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec sub-threshold swing at room temperature

First Demonstration of Vertically Stacked Gate-All-Around Highly Strained Germanium Nanowire pFETs

Junctionless versus inversion-mode lateral semiconductor nanowire transistors

Epitaxial diamond-hexagonal silicon nano-ribbon growth on (001) silicon

Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

Record GmSAT/SSSAT and PBTI Reliability in Si-Passivated Ge nFinFETs by Improved Gate-Stack Surface Preparation

Electrical Characteristics of p-Type Bulk Si Fin Field-Effect Transistor Using Solid-Source Doping With 1-nm Phosphosilicate Glass

3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability

Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

Holisitic device exploration for 7nm node

Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal

Strained Si CMOS (SS CMOS) technology: opportunities and challenges

Voltage Contrast Inspection Methodology for Inline Detection of Missing Spacer and Other Nonvisual Defects

A comparison of arsenic and phosphorus extension by Room Temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7nm) technology relevant fin dimensions

New electrical testing structures and analysis method for MOL and BEOL process diagnostics and TDDB reliability assessment

P80 Two different modalities to end a pregnancy with severe neurological fetal malformations

Record Gm SAT /SS SAT and PBTI Reliability in Si-Passivated Ge nFinFETs by Improved Gate-Stack Surface Preparation

Thermal Stability of TiN/Ti/p+-Si0.3Ge0.7 Contact With Ultralow Contact Resistivity

Thermal Stability of TiN/Ti/p + -Si 0.3 Ge 0.7 Contact With Ultralow Contact Resistivity

Thermal Stability of TiN/Ti/+-Si0.3Ge0.7 Contact With Ultralow Contact Resistivity

Demonstration of 2e12 cm^sup -2^ eV^sup -1^ 2D-oxide interface trap density on back-gated MoS^sub 2^ flake devices with 2.5 nm EOT

Demonstration of 2e12cm−2eV−1 2D-oxide interface trap density on back-gated MoS2 flake devices with 2.5nm EOT

Demonstration of 2e12 cm−2eV−1 2D-oxide interface trap density on back-gated MoS2 flake devices with 2.5 nm EOT

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