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Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

Solid-state electronics, 2010-09, Vol.54 (9), p.855-860

2010

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"Linear kink effect" induced by electron valence band tunneling in ultrathin gate oxide bulk and SOI MOSFETS

IEEE transactions on electron devices, 2003-07, Vol.50 (7), p.1675-1682

2003

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Design and Simulation of a 6-Bit Successive-Approximation ADC Using Modeled Organic Thin-Film Transistors

Active and Passive Electronic Components, 2016-01, Vol.2016, p.1-11

2016

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Low-frequency noise behavior of SiO2--HfO2 dual-layer gate dielectric nMOSFETs with different interfacial oxide thickness

IEEE transactions on electron devices, 2004-05, Vol.51 (5), p.780

2004

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A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS

IEEE journal of solid-state circuits, 2005-07, Vol.40 (7), p.1434-1442

2005

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Scalable and multibias high frequency modeling of multi-fin FETs

Solid-state electronics, 2006-11, Vol.50 (11-12), p.1780-1786

2006

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DC and low frequency noise performances of SOI p-FinFETs at very low temperature

Solid-state electronics, 2013-12, Vol.90, p.160-165

2013

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High-Frequency Noise Performance of 60-nm Gate-Length FinFETs

IEEE transactions on electron devices, 2008-10, Vol.55 (10), p.2718-2727

2008

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Low frequency noise characterization in n-channel FinFETs

Solid-state electronics, 2012-04, Vol.70, p.20-26

2012

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Low-frequency noise in silicon-on-insulator devices and technologies

Solid-state electronics, 2007-01, Vol.51 (1), p.16-37

2007

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Low temperature noise spectroscopy of 0.1 μ m partially depleted silicon on insulator metal-oxide-semiconductor field effect transistors

Journal of applied physics, 2007-05, Vol.101 (10), p.104511-104511-5

2007

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Y-Function Analysis of the Low Temperature Behavior of Ultrathin Film FD SOI MOSFETs

Active and Passive Electronic Components, 2014-01, Vol.2014 (2014), p.1-10

2014

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Correlation between the 1∕f noise parameters and the effective low-field mobility in HfO2 gate dielectric n-channel metal–oxide–semiconductor field-effect transistors

Applied physics letters, 2004-08, Vol.85 (6), p.1057-1059

2004

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Impact of fin width on digital and analog performances of n-FinFETs

Solid-state electronics, 2007-04, Vol.51 (4), p.551-559

2007

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Stochastic Matching Properties of FinFETs

IEEE electron device letters, 2006-10, Vol.27 (10), p.846-848

2006

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Matching Performance of FinFET Devices With Fin Widths Down to 10 nm

IEEE electron device letters, 2009-12, Vol.30 (12), p.1374-1376

2009

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A Two-Dimensional Model for Interface Coupling in Triple-Gate Transistors

IEEE transactions on electron devices, 2007-04, Vol.54 (4), p.767-775

2007

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Volltext

Determination and Validation of New Nonlinear FinFET Model Based on Lookup Tables

IEEE microwave and wireless components letters, 2007-05, Vol.17 (5), p.361-363

2007

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Volltext

Low-frequency noise overshoot in ultrathin gate oxide silicon-on-insulator metal–oxide–semiconductor field-effect transistors

Applied physics letters, 2003-03, Vol.82 (11), p.1790-1792

2003

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Holisitic device exploration for 7nm node

2015 IEEE Custom Integrated Circuits Conference (CICC), 2015, p.1-5

2015

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Modeling of Current-Voltage Characteristics of the Photoactivated Device Based on SOI Technology

Active and Passive Electronic Components, 2012-01, Vol.2012, p.1-7

2012

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Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs

Solid-state electronics, 2010-12, Vol.54 (12), p.1592-1597

2010

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Impact of line width roughness on the matching performances of next-generation devices

Thin solid films, 2008-04, Vol.516 (11), p.3690-3696

2008

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Light Sensor Platform Based on the Integration of Bacteriorhodopsin with a Single Electron Transistor

Active and Passive Electronic Components, 2011-01, Vol.2011, p.1-7

2011

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Vertical device architecture for 5nm and beyond: Device & circuit implications

IEEE Conferences, 2015, p.T26-T27

2015

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Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

"Linear kink effect" induced by electron valence band tunneling in ultrathin gate oxide bulk and SOI MOSFETS

Design and Simulation of a 6-Bit Successive-Approximation ADC Using Modeled Organic Thin-Film Transistors

Low-frequency noise behavior of SiO2--HfO2 dual-layer gate dielectric nMOSFETs with different interfacial oxide thickness

A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS

Scalable and multibias high frequency modeling of multi-fin FETs

DC and low frequency noise performances of SOI p-FinFETs at very low temperature

High-Frequency Noise Performance of 60-nm Gate-Length FinFETs

Low frequency noise characterization in n-channel FinFETs

Low-frequency noise in silicon-on-insulator devices and technologies

Low temperature noise spectroscopy of 0.1 μ m partially depleted silicon on insulator metal-oxide-semiconductor field effect transistors

Y-Function Analysis of the Low Temperature Behavior of Ultrathin Film FD SOI MOSFETs

Correlation between the 1∕f noise parameters and the effective low-field mobility in HfO2 gate dielectric n-channel metal–oxide–semiconductor field-effect transistors

Impact of fin width on digital and analog performances of n-FinFETs

Stochastic Matching Properties of FinFETs

Matching Performance of FinFET Devices With Fin Widths Down to 10 nm

A Two-Dimensional Model for Interface Coupling in Triple-Gate Transistors

Determination and Validation of New Nonlinear FinFET Model Based on Lookup Tables

Low-frequency noise overshoot in ultrathin gate oxide silicon-on-insulator metal–oxide–semiconductor field-effect transistors

Holisitic device exploration for 7nm node

Modeling of Current-Voltage Characteristics of the Photoactivated Device Based on SOI Technology

Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs

Impact of line width roughness on the matching performances of next-generation devices

Light Sensor Platform Based on the Integration of Bacteriorhodopsin with a Single Electron Transistor

Vertical device architecture for 5nm and beyond: Device & circuit implications

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