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Autonomous Fault Emulation: A New FPGA-Based Acceleration System for Hardness Evaluation

IEEE transactions on nuclear science, 2007-02, Vol.54 (1), p.252-261

2007

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Solar Energy Harvesting to Improve Capabilities of Wearable Devices

Sensors (Basel, Switzerland), 2022-05, Vol.22 (10), p.3950

2022

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Analysis of SET Effects in a PIC Microprocessor for Selective Hardening

IEEE transactions on nuclear science, 2011-06, Vol.58 (3), p.1078-1085

2011

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Extensive SEU Impact Analysis of a PIC Microprocessor for Selective Hardening

IEEE transactions on nuclear science, 2010-08, Vol.57 (4), p.1986-1991

2010

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Formal Verification of Fault-Tolerant Hardware Designs

IEEE access, 2023-01, Vol.11, p.1-1

2023

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SET Emulation Considering Electrical Masking Effects

IEEE transactions on nuclear science, 2009-08, Vol.56 (4), p.2021-2025

2009

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Hardening Architectures for Multiprocessor System-on-Chip

IEEE transactions on nuclear science, 2024-08, Vol.71 (8), p.1887-1895

2024

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Hybrid Hardening Approach for a Fault-Tolerant RISC-V System-On-Chip

IEEE transactions on nuclear science, 2024-08, Vol.71 (8), p.1722-1730

2024

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Evaluating Reduced Resolution Redundancy for Radiation Hardening in FPGA designs

IEEE transactions on nuclear science, 2023-08, Vol.70 (8), p.1-1

2023

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Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures

IEEE transactions on dependable and secure computing, 2011-03, Vol.8 (2), p.308-314

2011

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Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection

IEEE transactions on computers, 2012-03, Vol.61 (3), p.313-322

2012

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Analyzing the Influence of Memory and Workload on the Reliability of GPUs Under Neutron Radiation

IEEE transactions on nuclear science, 2024-08, Vol.71 (8), p.1487-1495

2024

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Sensitivity Evaluation Method for Aerospace Digital Systems With Collaborative Hardening

IEEE transactions on nuclear science, 2011-06, Vol.58 (3), p.1053-1058

2011

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Radiation Testing of a Multiprocessor Macrosynchronized Lockstep Architecture With FreeRTOS

IEEE transactions on nuclear science, 2022-03, Vol.69 (3), p.462-469

2022

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Analyzing Reduced Precision Triple Modular Redundancy Under Proton Irradiation

IEEE transactions on nuclear science, 2022-03, Vol.69 (3), p.470-477

2022

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Comparison of Parallel Implementation Strategies in GPU-Accelerated System-on-Chip Under Proton Irradiation

IEEE transactions on nuclear science, 2022-03, Vol.69 (3), p.444-452

2022

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Reliability Evaluation of LU Decomposition on GPU-Accelerated System-on-Chip Under Proton Irradiation

IEEE transactions on nuclear science, 2022-07, Vol.69 (7), p.1467-1474

2022

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Analyzing Scaled Reduced Precision Redundancy for Error Mitigation Under Proton Irradiation

IEEE transactions on nuclear science, 2022-07, Vol.69 (7), p.1485-1491

2022

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Analysis of Turbo Decoder Robustness Against SEU Effects

IEEE transactions on nuclear science, 2009-08, Vol.56 (4), p.2184-2188

2009

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Using Benchmarks for Radiation Testing of Microprocessors and FPGAs

IEEE transactions on nuclear science, 2015-12, Vol.62 (6), p.2547-2554

2015

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HW/SW Co-Simulation System for Enhancing Hardware-in-the-Loop of Power Converter Digital Controllers

IEEE journal of emerging and selected topics in power electronics, 2017-12, Vol.5 (4), p.1779-1786

2017

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SET Emulation Under a Quantized Delay Model

Journal of electronic testing, 2009-02, Vol.25 (1), p.107-116

2009

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Two Complementary Approaches for Studying the Effects of SEUs on Digital Processors

IEEE transactions on nuclear science, 2007-08, Vol.54 (4), p.924-928

2007

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SET Emulation Under a Quantized Delay Model

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007, p.68-78

2007

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Design Space Analysis for a Digital Lock-In Amplifier for Infrared Gas Sensor Signal Acquisition

2023 38th Conference on Design of Circuits and Integrated Systems (DCIS), 2023, p.1-6

2023

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Autonomous Fault Emulation: A New FPGA-Based Acceleration System for Hardness Evaluation

Solar Energy Harvesting to Improve Capabilities of Wearable Devices

Analysis of SET Effects in a PIC Microprocessor for Selective Hardening

Extensive SEU Impact Analysis of a PIC Microprocessor for Selective Hardening

Formal Verification of Fault-Tolerant Hardware Designs

SET Emulation Considering Electrical Masking Effects

Hardening Architectures for Multiprocessor System-on-Chip

Hybrid Hardening Approach for a Fault-Tolerant RISC-V System-On-Chip

Evaluating Reduced Resolution Redundancy for Radiation Hardening in FPGA designs

Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures

Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection

Analyzing the Influence of Memory and Workload on the Reliability of GPUs Under Neutron Radiation

Sensitivity Evaluation Method for Aerospace Digital Systems With Collaborative Hardening

Radiation Testing of a Multiprocessor Macrosynchronized Lockstep Architecture With FreeRTOS

Analyzing Reduced Precision Triple Modular Redundancy Under Proton Irradiation

Comparison of Parallel Implementation Strategies in GPU-Accelerated System-on-Chip Under Proton Irradiation

Reliability Evaluation of LU Decomposition on GPU-Accelerated System-on-Chip Under Proton Irradiation

Analyzing Scaled Reduced Precision Redundancy for Error Mitigation Under Proton Irradiation

Analysis of Turbo Decoder Robustness Against SEU Effects

Using Benchmarks for Radiation Testing of Microprocessors and FPGAs

HW/SW Co-Simulation System for Enhancing Hardware-in-the-Loop of Power Converter Digital Controllers

SET Emulation Under a Quantized Delay Model

Two Complementary Approaches for Studying the Effects of SEUs on Digital Processors

SET Emulation Under a Quantized Delay Model

Design Space Analysis for a Digital Lock-In Amplifier for Infrared Gas Sensor Signal Acquisition

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