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Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering

IEEE transactions on electron devices, 2005-05, Vol.52 (5), p.909-917

2005

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Fringing-Induced Drain Current Improvement in the Tunnel Field-Effect Transistor With High- \kappa Gate Dielectrics

IEEE transactions on electron devices, 2009-01, Vol.56 (1), p.100-108

2009

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Inflection Points in GAA NS-FET to C-FET Scaling Considering Impact of DTCO Boosters

IEEE transactions on electron devices, 2024-04, Vol.71 (4), p.2309-2314

2024

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Optimization and Benchmarking FinFETs and GAA Nanosheet Architectures at 3-nm Technology Node: Impact of Unique Boosters

IEEE transactions on electron devices, 2022-08, Vol.69 (8), p.4088-4094

2022

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Self-Heating in iN8-iN2 CMOS Logic Cells: Thermal Impact of Architecture (FinFET, Nanosheet, Forksheet and CFET) and Scaling Boosters

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.371-372

2022

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A simulation approach to optimize the electrical parameters of a vertical tunnel FET

IEEE transactions on electron devices, 2005-07, Vol.52 (7), p.1541-1547

2005

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Vertical tunnel field-effect transistor

IEEE transactions on electron devices, 2004-02, Vol.51 (2), p.279-282

2004

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Improved Reliability by Reduction of Hot-Electron Damage in the Vertical Impact-Ionization MOSFET (I-MOS)

IEEE electron device letters, 2007-01, Vol.28 (1), p.65-67

2007

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An Ultralow-Resistance Ultrashallow Metallic Source/Drain Contact Scheme for III-V NMOS

IEEE electron device letters, 2012-04, Vol.33 (4), p.501-503

2012

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P-Channel Tunnel Field-Effect Transistors down to Sub-50 nm Channel Lengths

Japanese Journal of Applied Physics, 2006-04, Vol.45 (4S), p.3106

2006

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Fabrication and Analysis of a / Heterojunction Line Tunnel FET

IEEE transactions on electron devices, 2014-03, Vol.61 (3), p.707-715

2014

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Growth of heterostructures on InAs for high mobility device applications

Journal of crystal growth, 2013-09, Vol.378, p.117-120

2013

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Indium arsenide (InAs) single and dual quantum-well heterostructure FinFETs

2015 Symposium on VLSI Technology (VLSI Technology), 2015, p.T208-T209

2015

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Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021, p.55-58

2021

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Co-integration Process Compatible Input/Output (I/O) Device Options for GAA Nanosheet Technology

ESSDERC 2022 - IEEE 52nd European Solid-State Device Research Conference (ESSDERC), 2022, p.265-268

2022

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InAs hole inversion and bandgap interface state density of 2 × 1011 cm−2 eV−1 at HfO2/InAs interfaces

Applied physics letters, 2013-09, Vol.103 (14)

2013

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Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks

ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC), 2021, p.55-58

2021

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Sub-50 nm high performance PDBFET with impact ionization

Thin solid films, 2006-06, Vol.508 (1), p.323-325

2006

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Characterizing the Changes in Material Use due to Vehicle Electrification

Environmental science & technology, 2021-07, Vol.55 (14), p.10097-10107

2021

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Gate-controlled resonant interband tunneling in silicon

Applied physics letters, 2004-09, Vol.85 (10), p.1707-1709

2004

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Comparative Study of High-k/GaSb Interfaces for Use in Antimonide Based MOSFETs

IEEE electron device letters, 2014, Vol.35 (1), p.21-23

2014

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InAs hole inversion and bandgap interface state density of 2 x 10(11) cm(-2) eV(-1) at HfO2/InAs interfaces

Applied physics letters, 2013-09, Vol.103 (14)

2013

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Inflection Points in Cfet Scaling: Impact of Dtco Boosters

2024 Conference of Science and Technology for Integrated Circuits (CSTIC), 2024, p.1-3

2024

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3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications

2018 IEEE International Electron Devices Meeting (IEDM), 2018, p.28.7.1-28.7.4

2018

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Characteristics and optimisation of vertical and planar tunnelling-FETs

Journal of physics. Conference series, 2005-01, Vol.10 (1), p.15-18

2005

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Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering

Fringing-Induced Drain Current Improvement in the Tunnel Field-Effect Transistor With High- \kappa Gate Dielectrics

Inflection Points in GAA NS-FET to C-FET Scaling Considering Impact of DTCO Boosters

Optimization and Benchmarking FinFETs and GAA Nanosheet Architectures at 3-nm Technology Node: Impact of Unique Boosters

Self-Heating in iN8-iN2 CMOS Logic Cells: Thermal Impact of Architecture (FinFET, Nanosheet, Forksheet and CFET) and Scaling Boosters

A simulation approach to optimize the electrical parameters of a vertical tunnel FET

Vertical tunnel field-effect transistor

Improved Reliability by Reduction of Hot-Electron Damage in the Vertical Impact-Ionization MOSFET (I-MOS)

An Ultralow-Resistance Ultrashallow Metallic Source/Drain Contact Scheme for III-V NMOS

P-Channel Tunnel Field-Effect Transistors down to Sub-50 nm Channel Lengths

Fabrication and Analysis of a / Heterojunction Line Tunnel FET

Growth of heterostructures on InAs for high mobility device applications

Indium arsenide (InAs) single and dual quantum-well heterostructure FinFETs

Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks

Co-integration Process Compatible Input/Output (I/O) Device Options for GAA Nanosheet Technology

InAs hole inversion and bandgap interface state density of 2 × 1011 cm−2 eV−1 at HfO2/InAs interfaces

Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks

Sub-50 nm high performance PDBFET with impact ionization

Characterizing the Changes in Material Use due to Vehicle Electrification

Gate-controlled resonant interband tunneling in silicon

Comparative Study of High-k/GaSb Interfaces for Use in Antimonide Based MOSFETs

InAs hole inversion and bandgap interface state density of 2 x 10(11) cm(-2) eV(-1) at HfO2/InAs interfaces

Inflection Points in Cfet Scaling: Impact of Dtco Boosters

3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications

Characteristics and optimisation of vertical and planar tunnelling-FETs

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