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Optimal negative sequence current suppression strategy without phase‐locked loop based on the control of clustered new energy power stations

IET generation, transmission & distribution, 2023-10, Vol.17 (19), p.4248-4257

2023

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A 5.91–8.94GHz phase‐locked loop in 65 nm CMOS for 5G applications

Microwave and optical technology letters, 2023-04, Vol.65 (4), p.975-980

2023

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Using tail current phase shift technique to improve locking range injection‐locked frequency divider

International journal of circuit theory and applications, 2023-08, Vol.51 (8), p.3596-3611

2023

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A 7.6–12.3 GHz wide‐band PLL with an ultra low reference spur −81.1 dBc in 0.13 μm CMOS technology

International journal of circuit theory and applications, 2023-07, Vol.51 (7), p.3003-3016

2023

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A (0.75-1.13)mW and (2.4-5.2)ps RMS jitter Integer-N based Dual-Loop PLL for Indoor and Outdoor Positioning in 28nm FD-SOI CMOS Technology

IEEE transactions on circuits and systems. II, Express briefs, 2023-07, p.1-1

2023

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A 224–448 MHz low‐power fully integrated phase‐locked loop using 0.18‐μm CMOS process

Microwave and optical technology letters, 2017-07, Vol.59 (7), p.1750-1755

2017

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Power Electronics in Renewable Energy Systems

2019

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A 5 GHz fully-integrated low-power phase-locked loop using 0.18-μm CMOS technology

Microwave and optical technology letters, 2016-07, Vol.58 (7), p.1534-1537

2016

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Comparative study of single-phase phase-locked loops for grid-connected inverters under non-ideal grid conditions

CSEE Journal of Power and Energy Systems, 2022-01, Vol.8 (1), p.155-164

2022

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77 GHz phase‐locked loop for automobile radar system in 90‐nm CMOS technology

Microwave and optical technology letters, 2018-03, Vol.60 (3), p.546-555

2018

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FPGA‐based implementation for improved control scheme of grid‐connected PV system with 3‐phase 3‐level NPC‐VSI

International journal of circuit theory and applications, 2018-04, Vol.46 (4), p.942-964

2018

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A Self-Biased Low-Jitter Process-Insensitive Phase-Locked Loop for 1.25Gb/s-6.25Gb/s SerDes

Chinese Journal of Electronics, 2018-09, Vol.27 (5), p.1009-1014

2018

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Spur reduction in frequency synthesizer with an array of switched capacitors

International journal of circuit theory and applications, 2015-12, Vol.43 (12), p.1815-1831

2015

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Multi-PLL with two-stage fusion to mitigate ionospheric scintillation effects on GPS receivers

Radio science, 2015-07, Vol.50 (7), p.630-641

2015

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Implementation of a low-cost phase-locked loop clock-recovery module for 40-Gb/s optical receivers

Microwave and optical technology letters, 2006-02, Vol.48 (2), p.312-315

2006

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Adaptive filtering with robust controller for improvement of inertial response of wind turbine

International transactions on electrical energy systems, 2019-10, Vol.29 (10), p.n/a

2019

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Analysis and effective controller design for the cascaded H-bridge multilevel APF with adaptive signal processing algorithms

International journal of circuit theory and applications, 2012-07, Vol.40 (7), p.635-659

2012

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On the simulation of fast settling charge pump PLLs up to fourth order

International journal of circuit theory and applications, 2011-12, Vol.39 (12), p.1257-1273

2011

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A 28.8-to-43.2 GHz 79.8 fs } Jitter and - 78.5 dBc Reference Spur PLL Exploiting Complementary Mixing Phase Detector With Mismatch Calibration

IEEE transactions on microwave theory and techniques, 2024-02, p.1-18

2024

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IEEE_Xplore

From 5g To 6g And Beyond: The 7 Cs Of Future Communications

Kiat Seng Yeo

2023

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A Radiation-Hardened 15-22-GHz Frequency Synthesizer in 22-nm FinFET

IEEE journal of solid-state circuits, 2024-03, p.1-14

2024

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IEEE_Xplore

A 6 to 12-GHz Fractional- N Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays

IEEE journal of solid-state circuits, 2024-03, p.1-13

2024

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IEEE_Xplore

Recent advances in synchronization techniques for grid-tied PV system: A review

Energy reports, 2021-11, Vol.7, p.6581-6599

2021

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Small-Signal Stability Analysis of Type-4 Wind in Series-Compensated Networks

IEEE transactions on energy conversion, 2019-09, Vol.35 (1)

2019

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A Fractional- N Sampling PLL With a Merged Constant-Slope DTC and Sampling PD

IEEE journal of solid-state circuits, 2024-02, p.1-11

2024

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IEEE_Xplore

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Optimal negative sequence current suppression strategy without phase‐locked loop based on the control of clustered new energy power stations

A 5.91–8.94GHz phase‐locked loop in 65 nm CMOS for 5G applications

Using tail current phase shift technique to improve locking range injection‐locked frequency divider

A 7.6–12.3 GHz wide‐band PLL with an ultra low reference spur −81.1 dBc in 0.13 μm CMOS technology

A (0.75-1.13)mW and (2.4-5.2)ps RMS jitter Integer-N based Dual-Loop PLL for Indoor and Outdoor Positioning in 28nm FD-SOI CMOS Technology

A 224–448 MHz low‐power fully integrated phase‐locked loop using 0.18‐μm CMOS process

Power Electronics in Renewable Energy Systems

A 5 GHz fully-integrated low-power phase-locked loop using 0.18-μm CMOS technology

Comparative study of single-phase phase-locked loops for grid-connected inverters under non-ideal grid conditions

77 GHz phase‐locked loop for automobile radar system in 90‐nm CMOS technology

FPGA‐based implementation for improved control scheme of grid‐connected PV system with 3‐phase 3‐level NPC‐VSI

A Self-Biased Low-Jitter Process-Insensitive Phase-Locked Loop for 1.25Gb/s-6.25Gb/s SerDes

Spur reduction in frequency synthesizer with an array of switched capacitors

Multi-PLL with two-stage fusion to mitigate ionospheric scintillation effects on GPS receivers

Implementation of a low-cost phase-locked loop clock-recovery module for 40-Gb/s optical receivers

Adaptive filtering with robust controller for improvement of inertial response of wind turbine

Analysis and effective controller design for the cascaded H-bridge multilevel APF with adaptive signal processing algorithms

On the simulation of fast settling charge pump PLLs up to fourth order

A 28.8-to-43.2 GHz 79.8 fs } Jitter and - 78.5 dBc Reference Spur PLL Exploiting Complementary Mixing Phase Detector With Mismatch Calibration

From 5g To 6g And Beyond: The 7 Cs Of Future Communications

A Radiation-Hardened 15-22-GHz Frequency Synthesizer in 22-nm FinFET

A 6 to 12-GHz Fractional- N Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays

Recent advances in synchronization techniques for grid-tied PV system: A review

Small-Signal Stability Analysis of Type-4 Wind in Series-Compensated Networks

A Fractional- N Sampling PLL With a Merged Constant-Slope DTC and Sampling PD

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