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Modeling of VSC Connected to Weak Grid for Stability Analysis of DC-Link Voltage Control

IEEE journal of emerging and selected topics in power electronics, 2015-12, Vol.3 (4), p.1193-1204

2015

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A Sub-mW 2.4-GHz Active-Mixer-Adopted Sub-Sampling PLL Achieving an FoM of −256 dB

IEEE journal of solid-state circuits, 2020-06, Vol.55 (6), p.1542-1552

2020

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A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO

IEEE journal of solid-state circuits, 2021-12, Vol.56 (12), p.3756-3767

2021

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Grid-Following DVI-Based Converter Operating in Weak Grids for Enhancing Frequency Stability

IEEE transactions on power delivery, 2022-02, Vol.37 (1), p.338-348

2022

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Impedance Reshaping Method of DFIG System Based on Compensating Rotor Current Dynamic to Eliminate PLL Influence

IEEE transactions on power electronics, 2024-04, p.1-11

2024

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Optimal negative sequence current suppression strategy without phase‐locked loop based on the control of clustered new energy power stations

IET generation, transmission & distribution, 2023-10, Vol.17 (19), p.4248-4257

2023

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A 19‐GHz low‐phase‐noise frequency synthesizer for a K‐band FMCW radar sensor of detecting micro unmanned aerial vehicles

Electronics letters, 2024-01, Vol.60 (2), p.n/a

2024

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Addressing DC Component in PLL and Notch Filter Algorithms

IEEE transactions on power electronics, 2012-01, Vol.27 (1), p.78-86

2012

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Grid-Synchronization Stability Analysis and Loop Shaping for PLL-Based Power Converters With Different Reactive Power Control

IEEE transactions on smart grid, 2020-01, Vol.11 (1), p.501-516

2020

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A 30-GHz Digital Sub-Sampling Fractional- N PLL With −238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS

IEEE journal of solid-state circuits, 2019-12, Vol.54 (12), p.3493-3502

2019

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A 5.91–8.94GHz phase‐locked loop in 65 nm CMOS for 5G applications

Microwave and optical technology letters, 2023-04, Vol.65 (4), p.975-980

2023

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Using tail current phase shift technique to improve locking range injection‐locked frequency divider

International journal of circuit theory and applications, 2023-08, Vol.51 (8), p.3596-3611

2023

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A 7.6–12.3 GHz wide‐band PLL with an ultra low reference spur −81.1 dBc in 0.13 μm CMOS technology

International journal of circuit theory and applications, 2023-07, Vol.51 (7), p.3003-3016

2023

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A SiGe Highly Integrated FMCW Transmitter Module With a 59.5-70.5-GHz Single Sweep Cover

IEEE transactions on microwave theory and techniques, 2018-09, Vol.66 (9), p.4121-4133

2018

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Analysis and Design of PLL Less Current Control for Weak Grid-Tied LCL-Type Voltage Source Converter

IEEE journal of emerging and selected topics in power electronics, 2022-08, Vol.10 (4), p.4026-4040

2022

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Small-Signal Model and Stability Control for Grid-Connected PV Inverter to a Weak Grid

Energies (Basel), 2021-07, Vol.14 (13), p.3907

2021

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A (0.75–1.13) mW and (2.4–5.2) ps RMS Jitter Integer-N-Based Dual-Loop PLL for Indoor and Outdoor Positioning in 28-nm FD-SOI CMOS Technology

IEEE transactions on circuits and systems. II, Express briefs, 2023-10, Vol.70 (10), p.3782-3786

2023

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28-nm FD-SOI CMOS Submilliwatt Ring Oscillator-Based Dual-Loop Integer-N PLL for 2.4-GHz Internet-of-Things Applications

IEEE transactions on microwave theory and techniques, 2022-04, Vol.70 (4), p.2207-2216

2022

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A (0.75-1.13)mW and (2.4-5.2)ps RMS jitter Integer-N based Dual-Loop PLL for Indoor and Outdoor Positioning in 28nm FD-SOI CMOS Technology

IEEE transactions on circuits and systems. II, Express briefs, 2023-07, p.1-1

2023

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A 16-GHz Background-Calibrated Duty-Cycled FMCW Charge-Pump PLL

IEEE journal of solid-state circuits, 2023, p.1-13

2023

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Bit Error Floor of MPSK in the Presence of Phase Error

IEEE transactions on vehicular technology, 2016-05, Vol.65 (5), p.3782-3786

2016

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Volltext

A 27.2-31.2 GHz 92-fs rms Integrated Jitter, Fractional- N Subsampling PLL Using Phase Rotating Technique in 65-nm CMOS

IEEE transactions on microwave theory and techniques, 2023-12, Vol.71 (12), p.1-12

2023

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A Low-Voltage PLL With a Supply-Noise Compensated Feedforward Ring VCO

IEEE transactions on circuits and systems. II, Express briefs, 2016-06, Vol.63 (6), p.548-552

2016

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A 224–448 MHz low‐power fully integrated phase‐locked loop using 0.18‐μm CMOS process

Microwave and optical technology letters, 2017-07, Vol.59 (7), p.1750-1755

2017

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A Novel Grid Synchronization Method Based On Hybrid Filter Under Distorted Voltage Conditions

IEEE access, 2020-01, Vol.8, p.1-1

2020

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Modeling of VSC Connected to Weak Grid for Stability Analysis of DC-Link Voltage Control

A Sub-mW 2.4-GHz Active-Mixer-Adopted Sub-Sampling PLL Achieving an FoM of −256 dB

A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO

Grid-Following DVI-Based Converter Operating in Weak Grids for Enhancing Frequency Stability

Impedance Reshaping Method of DFIG System Based on Compensating Rotor Current Dynamic to Eliminate PLL Influence

Optimal negative sequence current suppression strategy without phase‐locked loop based on the control of clustered new energy power stations

A 19‐GHz low‐phase‐noise frequency synthesizer for a K‐band FMCW radar sensor of detecting micro unmanned aerial vehicles

Addressing DC Component in PLL and Notch Filter Algorithms

Grid-Synchronization Stability Analysis and Loop Shaping for PLL-Based Power Converters With Different Reactive Power Control

A 30-GHz Digital Sub-Sampling Fractional- N PLL With −238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS

A 5.91–8.94GHz phase‐locked loop in 65 nm CMOS for 5G applications

Using tail current phase shift technique to improve locking range injection‐locked frequency divider

A 7.6–12.3 GHz wide‐band PLL with an ultra low reference spur −81.1 dBc in 0.13 μm CMOS technology

A SiGe Highly Integrated FMCW Transmitter Module With a 59.5-70.5-GHz Single Sweep Cover

Analysis and Design of PLL Less Current Control for Weak Grid-Tied LCL-Type Voltage Source Converter

Small-Signal Model and Stability Control for Grid-Connected PV Inverter to a Weak Grid

A (0.75–1.13) mW and (2.4–5.2) ps RMS Jitter Integer-N-Based Dual-Loop PLL for Indoor and Outdoor Positioning in 28-nm FD-SOI CMOS Technology

28-nm FD-SOI CMOS Submilliwatt Ring Oscillator-Based Dual-Loop Integer-N PLL for 2.4-GHz Internet-of-Things Applications

A (0.75-1.13)mW and (2.4-5.2)ps RMS jitter Integer-N based Dual-Loop PLL for Indoor and Outdoor Positioning in 28nm FD-SOI CMOS Technology

A 16-GHz Background-Calibrated Duty-Cycled FMCW Charge-Pump PLL

Bit Error Floor of MPSK in the Presence of Phase Error

A 27.2-31.2 GHz 92-fs rms Integrated Jitter, Fractional- N Subsampling PLL Using Phase Rotating Technique in 65-nm CMOS

A Low-Voltage PLL With a Supply-Noise Compensated Feedforward Ring VCO

A 224–448 MHz low‐power fully integrated phase‐locked loop using 0.18‐μm CMOS process

A Novel Grid Synchronization Method Based On Hybrid Filter Under Distorted Voltage Conditions

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