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Measuring the Gap Between FPGAs and ASICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-02, Vol.26 (2), p.203-215

2007

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IEEE_Xplore

NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-07, Vol.31 (7), p.994-1007

2012

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IEEE_Xplore

Anti-SAT: Mitigating SAT Attack on Logic Locking

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-02, Vol.38 (2), p.199-207

2019

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IEEE_Xplore

Accurate Simulation of High-Gain MMIC Amplifiers With Microstrip-Type Transistors

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-01, Vol.42 (1), p.16-26

2023

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IEEE_Xplore

Deep H-GCN: Fast Analog IC Aging-Induced Degradation Estimation

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-07, Vol.41 (7), p.1990-2003

2022

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IEEE_Xplore

The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis

IEEE transactions on computer-aided design of integrated circuits and systems, 2008-12, Vol.27 (12), p.2209-2222

2008

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IEEE_Xplore

Analytical Die-to-Die 3D Placement With Bistratal Wirelength Model and GPU Acceleration

IEEE transactions on computer-aided design of integrated circuits and systems, 2023, p.1-1

2023

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IEEE_Xplore

AccelTran: A Sparsity-Aware Accelerator for Dynamic Inference with Transformers

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-11, Vol.42 (11), p.1-1

2023

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IEEE_Xplore

Analog and Mixed-Signal IC Security via Sizing Camouflaging

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-05, Vol.40 (5), p.822-835

2021

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IEEE_Xplore

A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.4575-4586

2022

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IEEE_Xplore

TSV-Based 3-D ICs: Design Methods and Tools

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-10, Vol.36 (10), p.1593-1619

2017

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IEEE_Xplore

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-05, Vol.41 (5), p.1209-1221

2022

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IEEE_Xplore

TransCODE: Co-design of Transformers and Accelerators for Efficient Training and Inference

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-12, Vol.42 (12), p.1-1

2023

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IEEE_Xplore

An Artificial Neural Network Assisted Optimization System for Analog Design Space Exploration

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2640-2653

2020

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IEEE_Xplore

Highly Efficient Automatic Synthesis of a Millimeter-Wave On-Chip Deformable Spiral Inductor Using a Hybrid Knowledge-Guided and Data-Driven Technique

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-12, Vol.42 (12), p.1-1

2023

Link zum Volltext
IEEE_Xplore

MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method

IEEE transactions on computer-aided design of integrated circuits and systems, 2024, p.1-1

2024

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Verfügbarkeit prüfen

XBarNet: Computationally Efficient Memristor Crossbar Model Using Convolutional Autoencoder

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-12, Vol.41 (12), p.5489-5500

2022

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IEEE_Xplore

A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-09, Vol.40 (9), p.1952-1956

2021

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IEEE_Xplore

Golden-Free Robust Age Estimation to Triage Recycled ICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-09, Vol.42 (9), p.2839-2851

2023

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IEEE_Xplore

Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings

IEEE transactions on computer-aided design of integrated circuits and systems, 2010-04, Vol.29 (4), p.509-527

2010

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IEEE_Xplore

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2938-2951

2020

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IEEE_Xplore

A multiparameter moment-matching model-reduction approach for generating geometrically parameterized interconnect performance models

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-05, Vol.23 (5), p.678-693

2004

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IEEE_Xplore

The Detection of Open and Leakage Faults for Prebond TSV Test Based on Weak Current Source

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-09, Vol.41 (9), p.2768-2779

2022

Link zum Volltext
IEEE_Xplore

QuCTS-Single-Flux Quantum Clock Tree Synthesis

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-10, Vol.41 (10), p.3346-3358

2022

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IEEE_Xplore

Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-06, Vol.38 (6), p.989-1002

2019

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IEEE_Xplore

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Measuring the Gap Between FPGAs and ASICs

NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory

Anti-SAT: Mitigating SAT Attack on Logic Locking

Accurate Simulation of High-Gain MMIC Amplifiers With Microstrip-Type Transistors

Deep H-GCN: Fast Analog IC Aging-Induced Degradation Estimation

The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis

Analytical Die-to-Die 3D Placement With Bistratal Wirelength Model and GPU Acceleration

AccelTran: A Sparsity-Aware Accelerator for Dynamic Inference with Transformers

Analog and Mixed-Signal IC Security via Sizing Camouflaging

A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs

TSV-Based 3-D ICs: Design Methods and Tools

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization

TransCODE: Co-design of Transformers and Accelerators for Efficient Training and Inference

An Artificial Neural Network Assisted Optimization System for Analog Design Space Exploration

Highly Efficient Automatic Synthesis of a Millimeter-Wave On-Chip Deformable Spiral Inductor Using a Hybrid Knowledge-Guided and Data-Driven Technique

MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method

XBarNet: Computationally Efficient Memristor Crossbar Model Using Convolutional Autoencoder

A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC

Golden-Free Robust Age Estimation to Triage Recycled ICs

Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

A multiparameter moment-matching model-reduction approach for generating geometrically parameterized interconnect performance models

The Detection of Open and Leakage Faults for Prebond TSV Test Based on Weak Current Source

QuCTS-Single-Flux Quantum Clock Tree Synthesis

Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop

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