UB Paderborn / Katalog / Suche / in CDI

Measuring the Gap Between FPGAs and ASICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-02, Vol.26 (2), p.203-215

2007

Link zum Volltext
IEEE_Xplore

AccelTran: A Sparsity-Aware Accelerator for Dynamic Inference with Transformers

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-11, Vol.42 (11), p.1-1

2023

Link zum Volltext
IEEE_Xplore

NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-07, Vol.31 (7), p.994-1007

2012

Link zum Volltext
IEEE_Xplore

Anti-SAT: Mitigating SAT Attack on Logic Locking

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-02, Vol.38 (2), p.199-207

2019

Link zum Volltext
IEEE_Xplore

Deep H-GCN: Fast Analog IC Aging-Induced Degradation Estimation

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-07, Vol.41 (7), p.1990-2003

2022

Link zum Volltext
IEEE_Xplore

The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis

IEEE transactions on computer-aided design of integrated circuits and systems, 2008-12, Vol.27 (12), p.2209-2222

2008

Link zum Volltext
IEEE_Xplore

Analytical Die-to-Die 3D Placement With Bistratal Wirelength Model and GPU Acceleration

IEEE transactions on computer-aided design of integrated circuits and systems, 2023, p.1-1

2023

Link zum Volltext
IEEE_Xplore

A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.4575-4586

2022

Link zum Volltext
IEEE_Xplore

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-05, Vol.41 (5), p.1209-1221

2022

Link zum Volltext
IEEE_Xplore

TransCODE: Co-design of Transformers and Accelerators for Efficient Training and Inference

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-12, Vol.42 (12), p.1-1

2023

Link zum Volltext
IEEE_Xplore

Highly Efficient Automatic Synthesis of a Millimeter-Wave On-Chip Deformable Spiral Inductor Using a Hybrid Knowledge-Guided and Data-Driven Technique

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-12, Vol.42 (12), p.1-1

2023

Link zum Volltext
IEEE_Xplore

Analog and Mixed-Signal IC Security via Sizing Camouflaging

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-05, Vol.40 (5), p.822-835

2021

Link zum Volltext
IEEE_Xplore

MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method

IEEE transactions on computer-aided design of integrated circuits and systems, 2024, p.1-1

2024

Link zum Volltext

Verfügbarkeit prüfen

Golden-Free Robust Age Estimation to Triage Recycled ICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-09, Vol.42 (9), p.1-1

2023

Link zum Volltext
IEEE_Xplore

On Legalization of Die Bonding Bumps and Pads for 3D ICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-03, p.1-1

2024

Link zum Volltext
IEEE_Xplore

Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings

IEEE transactions on computer-aided design of integrated circuits and systems, 2010-04, Vol.29 (4), p.509-527

2010

Link zum Volltext
IEEE_Xplore

A multiparameter moment-matching model-reduction approach for generating geometrically parameterized interconnect performance models

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-05, Vol.23 (5), p.678-693

2004

Link zum Volltext
IEEE_Xplore

The Detection of Open and Leakage Faults for Prebond TSV Test Based on Weak Current Source

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-09, Vol.41 (9), p.2768-2779

2022

Link zum Volltext
IEEE_Xplore

QuCTS-Single-Flux Quantum Clock Tree Synthesis

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-10, Vol.41 (10), p.3346-3358

2022

Link zum Volltext
IEEE_Xplore

Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-06, Vol.38 (6), p.989-1002

2019

Link zum Volltext
IEEE_Xplore

Modeling the Dependency of Analog Circuit Performance Parameters on Manufacturing Process Variations With Applications in Sensitivity Analysis and Yield Prediction

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-01, Vol.41 (1), p.129-142

2022

Link zum Volltext
IEEE_Xplore

An Integrated Layout-Synthesis Approach for Analog ICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2008-07, Vol.27 (7), p.1179-1189

2008

Link zum Volltext
IEEE_Xplore

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

IEEE transactions on computer-aided design of integrated circuits and systems, 2009-01, Vol.28 (1), p.3-21

2009

Link zum Volltext
IEEE_Xplore

A Fast SIE Solver With Cut Set Analysis and Terminals as Supernodes for Interconnects

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-03, p.1-1

2024

Link zum Volltext
IEEE_Xplore

A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-04, Vol.38 (4), p.755-766

2019

Link zum Volltext
IEEE_Xplore

Menü

Weitere Dienste

Einstellungen

Measuring the Gap Between FPGAs and ASICs

AccelTran: A Sparsity-Aware Accelerator for Dynamic Inference with Transformers

NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory

Anti-SAT: Mitigating SAT Attack on Logic Locking

Deep H-GCN: Fast Analog IC Aging-Induced Degradation Estimation

The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis

Analytical Die-to-Die 3D Placement With Bistratal Wirelength Model and GPU Acceleration

A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization

TransCODE: Co-design of Transformers and Accelerators for Efficient Training and Inference

Highly Efficient Automatic Synthesis of a Millimeter-Wave On-Chip Deformable Spiral Inductor Using a Hybrid Knowledge-Guided and Data-Driven Technique

Analog and Mixed-Signal IC Security via Sizing Camouflaging

MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method

Golden-Free Robust Age Estimation to Triage Recycled ICs

On Legalization of Die Bonding Bumps and Pads for 3D ICs

Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings

A multiparameter moment-matching model-reduction approach for generating geometrically parameterized interconnect performance models

The Detection of Open and Leakage Faults for Prebond TSV Test Based on Weak Current Source

QuCTS-Single-Flux Quantum Clock Tree Synthesis

Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop

Modeling the Dependency of Analog Circuit Performance Parameters on Manufacturing Process Variations With Applications in Sensitivity Analysis and Yield Prediction

An Integrated Layout-Synthesis Approach for Analog ICs

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

A Fast SIE Solver With Cut Set Analysis and Terminals as Supernodes for Interconnects

A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICs

Aktive Filter

Suchergebnisse filtern