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Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode

IEEE transactions on computers, 2024-02, Vol.73 (2), p.1-13

2024

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Dedicated Instruction Set for Pattern-based Data Transfers: an Experimental Validation on Systems Containing In-Memory Computing Units

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-11, Vol.42 (11), p.1-1

2023

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Implementing Over 100 Command Codes for a High-Speed Hybrid Brain-Computer Interface Using Concurrent P300 and SSVEP Features

IEEE transactions on biomedical engineering, 2020-11, Vol.67 (11), p.3073-3082

2020

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Compact Instruction Set Extensions for Kyber

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-03, Vol.43 (3), p.1-1

2024

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RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems

IEEE transactions on very large scale integration (VLSI) systems, 2023-07, Vol.31 (7), p.980-992

2023

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Haswell: The Fourth-Generation Intel Core Processor

IEEE MICRO, 2014-03, Vol.34 (2), p.6-20

2014

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Back to Homogeneous Computing: A Tightly-Coupled Neuromorphic Processor With Neuromorphic ISA

IEEE transactions on parallel and distributed systems, 2023-11, Vol.34 (11), p.1-18

2023

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Multi-Brain Coding Expands the Instruction Set in SSVEP-Based Brain-Computer Interfaces

IEEE transactions on human-machine systems, 2023-10, Vol.53 (5), p.1-9

2023

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DSIP: A Scalable Inference Accelerator for Convolutional Neural Networks

IEEE journal of solid-state circuits, 2018-02, Vol.53 (2), p.605-618

2018

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In-memory Set Operations on Memristor Crossbar

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-12, Vol.42 (12), p.1-1

2023

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eQASM: An Executable Quantum Instruction Set Architecture

2019 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2019, p.224-237

2019

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ISA Extensions of Shuffling Against Side-channel Attacks

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-03, Vol.43 (3), p.1-1

2024

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Always-on Vision Processing Unit for Mobile Applications

IEEE MICRO, 2015-03, Vol.35 (2), p.56-66

2015

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Reduced Instruction Set Computers Then and Now

Computer (Long Beach, Calif.), 2017-12, Vol.50 (12), p.10-12

Patterson, David

2017

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DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge

IEEE journal of solid-state circuits, 2023-01, Vol.58 (1), p.203-215

2023

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Designing Calibration and Expressivity-Efficient Instruction Sets for Quantum Computing

2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), 2021, p.846-859

2021

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A Lightweight Posit Processing Unit for RISC-V Processors in Deep Neural Network Applications

IEEE transactions on emerging topics in computing, 2022-10, Vol.10 (4), p.1898-1908

2022

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RISC-V Instruction Set Architecture Extensions: A Survey

IEEE access, 2023-01, Vol.11, p.1-1

2023

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Exact and approximate algorithms for the extension of embedded processor instruction sets

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-07, Vol.25 (7), p.1209-1229

2006

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Accelerating Deep Learning Inference in Constrained Embedded Devices Using Hardware Loops and a Dot Product Unit

IEEE access, 2020, Vol.8, p.165913-165926

2020

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The Design of Optimized RISC Processor for Edge Artificial Intelligence based on Custom Instruction Set Extension

IEEE access, 2023-01, Vol.11, p.1-1

2023

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A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance

IEEE journal of solid-state circuits, 2023-01, Vol.58 (1), p.216-226

2023

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r-map: Relating Implementation and Specification in Hardware Refinement Checking

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-12, Vol.42 (12), p.1-1

2023

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Scaling to the end of silicon with EDGE architectures

Computer (Long Beach, Calif.), 2004-07, Vol.37 (7), p.44-55

2004

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Enhancing a Near-Term Quantum Accelerator's Instruction Set Architecture for Materials Science Applications

IEEE transactions on quantum engineering, 2020, Vol.1, p.1-7

2020

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Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode

Dedicated Instruction Set for Pattern-based Data Transfers: an Experimental Validation on Systems Containing In-Memory Computing Units

Implementing Over 100 Command Codes for a High-Speed Hybrid Brain-Computer Interface Using Concurrent P300 and SSVEP Features

Compact Instruction Set Extensions for Kyber

RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems

Haswell: The Fourth-Generation Intel Core Processor

Back to Homogeneous Computing: A Tightly-Coupled Neuromorphic Processor With Neuromorphic ISA

Multi-Brain Coding Expands the Instruction Set in SSVEP-Based Brain-Computer Interfaces

DSIP: A Scalable Inference Accelerator for Convolutional Neural Networks

In-memory Set Operations on Memristor Crossbar

eQASM: An Executable Quantum Instruction Set Architecture

ISA Extensions of Shuffling Against Side-channel Attacks

Always-on Vision Processing Unit for Mobile Applications

Reduced Instruction Set Computers Then and Now

DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge

Designing Calibration and Expressivity-Efficient Instruction Sets for Quantum Computing

A Lightweight Posit Processing Unit for RISC-V Processors in Deep Neural Network Applications

RISC-V Instruction Set Architecture Extensions: A Survey

Exact and approximate algorithms for the extension of embedded processor instruction sets

Accelerating Deep Learning Inference in Constrained Embedded Devices Using Hardware Loops and a Dot Product Unit

The Design of Optimized RISC Processor for Edge Artificial Intelligence based on Custom Instruction Set Extension

A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance

r-map: Relating Implementation and Specification in Hardware Refinement Checking

Scaling to the end of silicon with EDGE architectures

Enhancing a Near-Term Quantum Accelerator's Instruction Set Architecture for Materials Science Applications

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