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Detailed Placement for Dedicated LUT-Level FPGA Interconnect

ACM transactions on reconfigurable technology and systems, 2022-12, Vol.15 (4), p.1-33, Article 37

2022

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Evaluating FPGA clusters under wide ranges of design parameters

2017 27th International Conference on Field Programmable Logic and Applications (FPL), 2017, p.1-8

2017

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Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming

2021 31st International Conference on Field-Programmable Logic and Applications (FPL), 2021, p.327-333

2021

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Automatic wire modeling to explore novel FPGA architectures

2016 International Conference on Field-Programmable Technology (FPT), 2016, p.181-184

2016

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Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths

2020 30th International Conference on Field-Programmable Logic and Applications (FPL), 2020, p.153-161

2020

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Finding a Needle in the Haystack of Hardened Interconnect Patterns

2019 29th International Conference on Field Programmable Logic and Applications (FPL), 2019, p.31-37

2019

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An Ant Colony Optimization Heuristic to Optimize Prediction of Stability of Object-Oriented Components

2015 IEEE International Conference on Information Reuse and Integration, 2015, p.225-228

2015

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NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element

Proceedings of the 2017 ACM/SIGDA International Symposium on field-programmable gate arrays, 2017, p.135-140

2017

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Revisiting and-inverter cones

Proceedings of the 2014 ACM/SIGDA international symposium on field-programmable gate arrays, 2014, p.45-54

2014

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Improved carry chain mapping for the VTR flow

2015 International Conference on Field Programmable Technology (FPT), 2015, p.80-87

2015

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Shadow And-Inverter Cones

2013 23rd International Conference on Field programmable Logic and Applications, 2013, p.1-4

2013

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A technology mapper for depth-constrained FPGA logic cells

2015 25th International Conference on Field Programmable Logic and Applications (FPL), 2015, p.1-8

2015

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Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only)

Proceedings of the ACM/SIGDA international symposium on field programmable gate arrays, 2013, p.279-279

2013

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Reducing the pressure on routing resources of FPGAs with generic logic chains

Proceedings of the 19th ACM/SIGDA international symposium on field programmable gate arrays, 2011, p.237-246

2011

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Detailed Placement for Dedicated LUT-Level FPGA Interconnect

Evaluating FPGA clusters under wide ranges of design parameters

Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming

Automatic wire modeling to explore novel FPGA architectures

Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths

Finding a Needle in the Haystack of Hardened Interconnect Patterns

An Ant Colony Optimization Heuristic to Optimize Prediction of Stability of Object-Oriented Components

NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element

Revisiting and-inverter cones

Improved carry chain mapping for the VTR flow

Shadow And-Inverter Cones

A technology mapper for depth-constrained FPGA logic cells

Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only)

Reducing the pressure on routing resources of FPGAs with generic logic chains

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