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Breaking the von Neumann bottleneck: architecture-level processing-in-memory technology

Science China. Information sciences, 2021-06, Vol.64 (6), p.160404, Article 160404

2021

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FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks

2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2017, p.553-564

2017

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moDNN: Memory Optimal Deep Neural Network Training on Graphics Processing Units

IEEE transactions on parallel and distributed systems, 2019-03, Vol.30 (3), p.646-661

2019

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Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs

IEEE transactions on very large scale integration (VLSI) systems, 2013-02, Vol.21 (2), p.239-249

2013

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Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs

IEEE transactions on circuits and systems. I, Regular papers, 2019-05, Vol.66 (5), p.1780-1793

2019

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ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels

IEEE transactions on very large scale integration (VLSI) systems, 2014-01, Vol.22 (1), p.113-126

2014

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An Analytical Framework for Estimating Scale-Out and Scale-Up Power Efficiency of Heterogeneous Manycores

IEEE transactions on computers, 2016-02, Vol.65 (2), p.367-381

2016

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C-Brain: A deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, p.1-6

2016

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DeepBurning-SEG: Generating DNN Accelerators of Segment-Grained Pipeline Architecture

2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), 2022, p.1396-1413

2022

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EcoUp: Towards Economical Datacenter Upgrading

IEEE transactions on parallel and distributed systems, 2016-07, Vol.27 (7), p.1968-1981

2016

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VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache

IEEE transactions on very large scale integration (VLSI) systems, 2016-03, Vol.24 (3), p.858-870

2016

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STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator

IEEE transactions on very large scale integration (VLSI) systems, 2017-04, Vol.25 (4), p.1285-1296

2017

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Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation

IEEE transactions on very large scale integration (VLSI) systems, 2016-01, Vol.24 (1), p.92-102

2016

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Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction

IEEE transactions on very large scale integration (VLSI) systems, 2013-05, Vol.21 (5), p.821-833

2013

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DeepBurning: Automatic generation of FPGA-based learning accelerators for the Neural Network family

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, p.1-6

2016

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On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems

IEEE transactions on very large scale integration (VLSI) systems, 2009-09, Vol.17 (9), p.1173-1186

2009

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PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM

IEEE transactions on very large scale integration (VLSI) systems, 2016-05, Vol.24 (5), p.1613-1625

2016

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Test-Quality Optimization for Variable n -Detections of Transition Faults

IEEE transactions on very large scale integration (VLSI) systems, 2014-08, Vol.22 (8), p.1738-1749

2014

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An abacus turn model for time/space-efficient reconfigurable routing

2011 38th Annual International Symposium on Computer Architecture (ISCA), 2011, p.259-270

2011

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ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation

IEEE transactions on computers, 2011-09, Vol.60 (9), p.1219-1232

2011

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RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors

IEEE transactions on very large scale integration (VLSI) systems, 2015-12, Vol.23 (12), p.3053-3064

2015

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SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation

IEEE transactions on very large scale integration (VLSI) systems, 2011-09, Vol.19 (9), p.1627-1640

2011

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PowerTrader: Enforcing Autonomous Power Management for Future Large-Scale Many-Core Processors

IEEE transactions on multi-scale computing systems, 2017-10, Vol.3 (4), p.283-295

2017

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Exploiting the Potential of Computation Reuse Through Approximate Computing

IEEE transactions on multi-scale computing systems, 2017-07, Vol.3 (3), p.152-165

2017

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Load Balance Guaranteed Vehicle-to-Vehicle Computation Offloading for Min-Max Fairness in VANETs

IEEE transactions on intelligent transportation systems, 2022-08, Vol.23 (8), p.11994-12013

2022

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Breaking the von Neumann bottleneck: architecture-level processing-in-memory technology

FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks

moDNN: Memory Optimal Deep Neural Network Training on Graphics Processing Units

Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs

Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs

ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels

An Analytical Framework for Estimating Scale-Out and Scale-Up Power Efficiency of Heterogeneous Manycores

C-Brain: A deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization

DeepBurning-SEG: Generating DNN Accelerators of Segment-Grained Pipeline Architecture

EcoUp: Towards Economical Datacenter Upgrading

VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache

STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator

Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation

Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction

DeepBurning: Automatic generation of FPGA-based learning accelerators for the Neural Network family

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems

PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM

Test-Quality Optimization for Variable n -Detections of Transition Faults

An abacus turn model for time/space-efficient reconfigurable routing

ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation

RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors

SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation

PowerTrader: Enforcing Autonomous Power Management for Future Large-Scale Many-Core Processors

Exploiting the Potential of Computation Reuse Through Approximate Computing

Load Balance Guaranteed Vehicle-to-Vehicle Computation Offloading for Min-Max Fairness in VANETs

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