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A 6T SRAM Based Two-Dimensional Configurable Challenge-Response PUF for Portable Devices

IEEE transactions on circuits and systems. I, Regular papers, 2022-06, Vol.69 (6), p.2542-2552

2022

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A 0.016 mV/mA Cross-Regulation 5-Output SIMO DC-DC Buck Converter Using Output-Voltage-Aware Charge Control Scheme

IEEE transactions on power electronics, 2018-11, Vol.33 (11), p.9619-9630

2018

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Efficient Maximum Power Point Tracking for a Distributed PV System under Rapidly Changing Environmental Conditions

IEEE transactions on power electronics, 2015-08, Vol.30 (8), p.4209-4218

2015

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A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS

IEEE journal of solid-state circuits, 2014-12, Vol.49 (12), p.2976-2989

2014

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A 0.5 V 8-12 Bit 300 KSPS SAR ADC With Adaptive Conversion Time Detection-and-Control for High Immunity to PVT Variations

IEEE access, 2020, Vol.8, p.101359-101368

2020

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Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks

IEEE journal of solid-state circuits, 2021-07, Vol.56 (7), p.2221-2233

2021

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An 88% Efficiency 0.1-300- \mu W Energy Harvesting System With 3-D MPPT Using Switch Width Modulation for IoT Smart Nodes

IEEE journal of solid-state circuits, 2018-10, Vol.53 (10), p.2751-2762

2018

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Energy-efficient Spread Second Capacitor Capacitive DAC for SAR ADC

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2017, 17(6), 78, pp.786-791

2017

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A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks

IEEE journal of solid-state circuits, 2022-11, Vol.57 (11), p.3466-3476

2022

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A Return-to-zero DAC with Tri-state Switching Scheme for Multiple Nyquist Operations

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2017, 17(3), 75, pp.378-386

2017

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A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for Processing Neural Networks

IEEE transactions on circuits and systems. I, Regular papers, 2021-02, Vol.68 (2), p.667-679

2021

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An 88% Efficiency 0.1–300-[Formula Omitted]W Energy Harvesting System With 3-D MPPT Using Switch Width Modulation for IoT Smart Nodes

IEEE journal of solid-state circuits, 2018-01, Vol.53 (10), p.2751

2018

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A 0.506-pJ 16-kb 8T SRAM With Vertical Read Wordlines and Selective Dual Split Power Lines

IEEE transactions on very large scale integration (VLSI) systems, 2020-06, Vol.28 (6), p.1345-1356

2020

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A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019, p.345-348

2019

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A 10-Bit, 50 MS/s, 55 fJ/conversion-step SAR ADC with split capacitor array

2011 9th IEEE International Conference on ASIC, 2011, p.472-475

2011

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A 137-μW 1.78-mm 2 30-Frames/s Real-Time Gesture Recognition SoC for Smart Devices

IEEE transactions on very large scale integration (VLSI) systems, 2020-08, Vol.28 (8), p.1909-1919

2020

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A 137-μW 1.78-mm2 30-Frames/s Real-Time Gesture Recognition SoC for Smart Devices

IEEE transactions on very large scale integration (VLSI) systems, 2020-08, Vol.28 (8), p.1909-1919

2020

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An 88% efficiency MPPT for PV energy harvesting system with novel switch width modulation for output power 100nW to 0.3mW

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2017, p.117-120

2017

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A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks

2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2019, p.1-6

2019

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A 12-bit Multi-Channel R-R DAC Using a Shared Resistor String Scheme for Area-Efficient Display Source Driver

IEEE transactions on circuits and systems. I, Regular papers, 2018-11, Vol.65 (11), p.3688-3697

2018

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A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC

2020 IEEE Custom Integrated Circuits Conference (CICC), 2020, p.1-4

2020

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A 213.7-µW Gesture Sensing System-On-Chip With Self-Adaptive Motion Detection and Noise-Tolerant Outermost-Edge-Based Feature Extraction in 65 nm

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019, p.123-126

2019

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A 213.7- \mu W Gesture Sensing System-On-Chip With Self-Adaptive Motion Detection and Noise-Tolerant Outermost-Edge-Based Feature Extraction in 65 nm

IEEE solid-state circuits letters, 2019-09, Vol.2 (9), p.123-126

2019

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A 16×128 stochastic-binary processing element array for accelerating stochastic dot-product computation using 1-16 bit-stream length

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, p.678-681

2020

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A 213.7-[Formula Omitted]W Gesture Sensing System-On-Chip With Self-Adaptive Motion Detection and Noise-Tolerant Outermost-Edge-Based Feature Extraction in 65 nm

IEEE solid-state circuits letters, 2019-01, Vol.2 (9), p.123

2019

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A 6T SRAM Based Two-Dimensional Configurable Challenge-Response PUF for Portable Devices

A 0.016 mV/mA Cross-Regulation 5-Output SIMO DC-DC Buck Converter Using Output-Voltage-Aware Charge Control Scheme

Efficient Maximum Power Point Tracking for a Distributed PV System under Rapidly Changing Environmental Conditions

A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS

A 0.5 V 8-12 Bit 300 KSPS SAR ADC With Adaptive Conversion Time Detection-and-Control for High Immunity to PVT Variations

Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks

An 88% Efficiency 0.1-300- \mu W Energy Harvesting System With 3-D MPPT Using Switch Width Modulation for IoT Smart Nodes

Energy-efficient Spread Second Capacitor Capacitive DAC for SAR ADC

A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks

A Return-to-zero DAC with Tri-state Switching Scheme for Multiple Nyquist Operations

A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for Processing Neural Networks

An 88% Efficiency 0.1–300-[Formula Omitted]W Energy Harvesting System With 3-D MPPT Using Switch Width Modulation for IoT Smart Nodes

A 0.506-pJ 16-kb 8T SRAM With Vertical Read Wordlines and Selective Dual Split Power Lines

A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation

A 10-Bit, 50 MS/s, 55 fJ/conversion-step SAR ADC with split capacitor array

A 137-μW 1.78-mm 2 30-Frames/s Real-Time Gesture Recognition SoC for Smart Devices

A 137-μW 1.78-mm2 30-Frames/s Real-Time Gesture Recognition SoC for Smart Devices

An 88% efficiency MPPT for PV energy harvesting system with novel switch width modulation for output power 100nW to 0.3mW

A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks

A 12-bit Multi-Channel R-R DAC Using a Shared Resistor String Scheme for Area-Efficient Display Source Driver

A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC

A 213.7-µW Gesture Sensing System-On-Chip With Self-Adaptive Motion Detection and Noise-Tolerant Outermost-Edge-Based Feature Extraction in 65 nm

A 213.7- \mu W Gesture Sensing System-On-Chip With Self-Adaptive Motion Detection and Noise-Tolerant Outermost-Edge-Based Feature Extraction in 65 nm

A 16×128 stochastic-binary processing element array for accelerating stochastic dot-product computation using 1-16 bit-stream length

A 213.7-[Formula Omitted]W Gesture Sensing System-On-Chip With Self-Adaptive Motion Detection and Noise-Tolerant Outermost-Edge-Based Feature Extraction in 65 nm

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