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Redox-Responsive Protein Design: Design of a Small Protein Motif Dependent on Glutathionylation

Biochemistry (Easton), 2018-12, Vol.57 (51), p.6956-6963

2018

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A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling

IEEE journal of solid-state circuits, 2022-01, Vol.57 (1), p.182-197

2022

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Analysis and Modeling of DC Current Crowding for TSV-Based 3-D Connections and Power Integrity

IEEE transactions on components, packaging, and manufacturing technology (2011), 2014-01, Vol.4 (1), p.123-133

2014

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A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias

2012 IEEE International Solid-State Circuits Conference, 2012, p.186-187

2012

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RaPiD: AI Accelerator for Ultra-low Precision Training and Inference

2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), 2021, p.153-166

2021

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Management von Forschungsverbünden: Möglichkeiten der Professionalisierung und Unterstützung

2008

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Forschungsverbundmanagement: Handbuch für die Gestaltung inter- und transdiziplinärer Projekte

2006

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Arginine Mimetics via α-Guanidino Acids: Introduction of Functional Groups and Stereochemistry Adjacent to Recognition Guanidiniums in Peptides

Chembiochem : a European journal of chemical biology, 2011-12, Vol.13 (2), p.259-270

2011

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A Scalable Multi-TeraOPS Core for AI Training and Inference

IEEE solid-state circuits letters, 2018-12, Vol.1 (12), p.217-220

2018

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9.1 A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.144-146

2021

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Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs

DAC Design Automation Conference 2012, 2012, p.157-162

2012

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A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference

2018 IEEE Symposium on VLSI Circuits, 2018, p.35-36

2018

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Design and Modeling Methodology of Vertical Interconnects for 3DI Applications

IEEE transactions on components, packaging, and manufacturing technology (2011), 2011-02, Vol.1 (2), p.163-167

2011

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Decoupling capacitor modeling and characterization for power supply noise in 3D systems

2012 SEMI Advanced Semiconductor Manufacturing Conference, 2012, p.414-419

2012

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Physical design of a fourth-generation POWER GHz microprocessor

2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), 2001, p.232-233

2001

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Design and Modeling Methodology of Vertical Interconnects for 3DI Applications : THROUGH SILICON VIAS

IEEE transactions on components, packaging, and manufacturing technology (2011), 2011, Vol.1 (1-2), p.163-167

2011

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Design, CAD and technology challenges for future processors: 3D perspectives

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 2011, p.212-212

2011

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Anomalous voltage overshoot during turn-off of thin-film n-channel SOI MOSFETs

IEEE electron device letters, 1993-04, Vol.14 (4), p.164-166

1993

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Intelligente Steuerung der Forschung durch Evaluation

Psychologische Rundschau, 2003, Vol.54 (4), p.246-248

2003

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Die Liebe ist kein Engelchen mit Fluegeln: Das alte Thema - im Spiegel von Liebesgeschichten Jugendlicher

Katechetische Blätter, 1985, Vol.110 (8), p.633-637

Scheuermann, Michael

1985

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Thermo-Compression Bonding and Mass Reflow Assembly Processes of 3D Logic Die Stacks

2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 2017, p.116-122

2017

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Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs

Proceedings of the International Conference on computer-aided design, 2013, p.363-370

2013

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Modeling of power delivery into 3D chips on silicon interposer

2012 IEEE 62nd Electronic Components and Technology Conference, 2012, p.683-689

2012

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Redox-Responsive Protein Design: Design of a Small Protein Motif Dependent on Glutathionylation

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling

Analysis and Modeling of DC Current Crowding for TSV-Based 3-D Connections and Power Integrity

A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias

Efficient AI System Design With Cross-Layer Approximate Computing

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference

Management von Forschungsverbünden: Möglichkeiten der Professionalisierung und Unterstützung

Forschungsverbundmanagement: Handbuch für die Gestaltung inter- und transdiziplinärer Projekte

Arginine Mimetics via α-Guanidino Acids: Introduction of Functional Groups and Stereochemistry Adjacent to Recognition Guanidiniums in Peptides

A Scalable Multi-TeraOPS Core for AI Training and Inference

9.1 A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling

Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs

A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference

Design and Modeling Methodology of Vertical Interconnects for 3DI Applications

Decoupling capacitor modeling and characterization for power supply noise in 3D systems

Physical design of a fourth-generation POWER GHz microprocessor

Design and Modeling Methodology of Vertical Interconnects for 3DI Applications : THROUGH SILICON VIAS

Design, CAD and technology challenges for future processors: 3D perspectives

Anomalous voltage overshoot during turn-off of thin-film n-channel SOI MOSFETs

Intelligente Steuerung der Forschung durch Evaluation

A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference

Die Liebe ist kein Engelchen mit Fluegeln: Das alte Thema - im Spiegel von Liebesgeschichten Jugendlicher

Thermo-Compression Bonding and Mass Reflow Assembly Processes of 3D Logic Die Stacks

Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs

Modeling of power delivery into 3D chips on silicon interposer

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