UB Paderborn / Katalog / Suche / in CDI

Sortiert nach

Einfacher Volltextzugriff von (fast) überall

Installieren Sie die LibKey Nomad-Browsererweiterung und erhalten Sie von vielen Webseiten einfachen Zugriff auf lizenzierte Volltexte oder Open Access Publikationen. Mehr erfahren...

Nanotube Junctionless FET: Proposal, Design, and Investigation

IEEE transactions on electron devices, 2017-04, Vol.64 (4), p.1851-1856

2017

Volltextzugriff (PDF)

Controlling L-BTBT and Volume Depletion in Nanowire JLFETs Using Core-Shell Architecture

IEEE transactions on electron devices, 2016-09, Vol.63 (9), p.3790-3794

2016

Volltextzugriff (PDF)

Junctionless Field-Effect Transistors: Design, Modeling, and Simulation

1st edition., 2019

Volltextzugriff (PDF)

Realizing Efficient Volume Depletion in SOI Junctionless FETs

IEEE journal of the Electron Devices Society, 2016-05, Vol.4 (3), p.110-115

2016

Volltextzugriff (PDF)

Analytical Modeling of Threshold Voltage and Subthreshold Slope for 3-D NAND Flash Memory With a Non-Uniform Doping Profile

IEEE journal of the Electron Devices Society, 2023, Vol.11, p.611-618

2023

Volltextzugriff (PDF)

Comprehensive Analysis of Gate-Induced Drain Leakage in Emerging FET Architectures: Nanotube FETs Versus Nanowire FETs

IEEE access, 2017-01, Vol.5, p.18918-18926

2017

Volltextzugriff (PDF)

Efficient Implementation of Mahalanobis Distance on Ferroelectric FinFET Crossbar for Outlier Detection

IEEE journal of the Electron Devices Society, 2024, Vol.12, p.516-524

2024

Volltextzugriff (PDF)

Controlling L-BTBT in Emerging Nanotube FETs Using Dual-Material Gate

IEEE journal of the Electron Devices Society, 2018-01, Vol.6, p.611-621

2018

Volltextzugriff (PDF)

Analytical Modeling of 3D NAND Flash Cell with a Gaussian Doping Profile

IEEE access, 2022, Vol.10, p.1-1

2022

Volltextzugriff (PDF)

Energy-Efficient Moderate Precision Time-Domain Mixed-Signal Vector-by-Matrix Multiplier Exploiting 1T-1R Arrays

IEEE journal on exploratory solid-state computational devices and circuits, 2020-06, Vol.6 (1), p.18-26

2020

Volltextzugriff (PDF)

Controlling the Drain Side Tunneling Width to Reduce Ambipolar Current in Tunnel FETs Using Heterodielectric BOX

IEEE transactions on electron devices, 2015-11, Vol.62 (11), p.3882-3886

2015

Volltextzugriff (PDF)

A Behavioral Compact Model for Static Characteristics of 3D NAND Flash Memory

IEEE electron device letters, 2019-04, Vol.40 (4), p.558-561

2019

Volltextzugriff (PDF)

Physical Insights Into the Nature of Gate-Induced Drain Leakage in Ultrashort Channel Nanowire FETs

IEEE transactions on electron devices, 2017-06, Vol.64 (6), p.2604-2610

2017

Volltextzugriff (PDF)

Recent trends in hardware security exploiting hybrid CMOS-resistive memory circuits

Semiconductor science and technology, 2017-12, Vol.32 (12), p.123001

2017

Volltextzugriff (PDF)

Parasitic Capacitance Model for Stacked Gate-All-Around Nanosheet FETs

IEEE transactions on electron devices, 2024-01, Vol.71 (1), p.1-9

2024

Volltextzugriff (PDF)

Parasitic Gate Capacitance Model for N-Stack Forksheet FETs

IEEE transactions on electron devices, 2024-03, Vol.71 (3), p.1728-1736

2024

Volltextzugriff (PDF)

Hybrid CMOS-RRAM True Random Number Generator Exploiting Coupled Entropy Sources

IEEE transactions on electron devices, 2023-03, Vol.70 (3), p.1-6

2023

Volltextzugriff (PDF)

Long Short-Term Memory Implementation Exploiting Passive RRAM Crossbar Array

IEEE transactions on electron devices, 2022-04, Vol.69 (4), p.1743-1751

2022

Volltextzugriff (PDF)

Diameter Dependence of Leakage Current in Nanowire Junctionless Field Effect Transistors

IEEE transactions on electron devices, 2017-03, Vol.64 (3), p.1330-1335

2017

Volltextzugriff (PDF)

Insight into Lateral Band-to-Band-Tunneling in Nanowire Junctionless FETs

IEEE transactions on electron devices, 2016-10, Vol.63 (10), p.4138-4142

2016

Volltextzugriff (PDF)

Spacer Design Guidelines for Nanowire FETs From Gate-Induced Drain Leakage Perspective

IEEE transactions on electron devices, 2017-07, Vol.64 (7), p.3007-3015

2017

Volltextzugriff (PDF)

Hybrid CMOS-Ferroelectric FET-Based Image Sensor With Tunable Dynamic Range

IEEE transactions on electron devices, 2024-01, Vol.71 (1), p.624-629

2024

Volltextzugriff (PDF)

Hardware Security Primitive Exploiting Intrinsic Variability in Analog Behavior of 3-D NAND Flash Memory Array

IEEE transactions on electron devices, 2019-05, Vol.66 (5), p.2158-2164

2019

Volltextzugriff (PDF)

Controlling BTBT-Induced Parasitic BJT Action in Junctionless FETs Using a Hybrid Channel

IEEE transactions on electron devices, 2016-08, Vol.63 (8), p.3350-3353

2016

Volltextzugriff (PDF)

Nanotube Tunneling FET With a Core Source for Ultrasteep Subthreshold Swing: A Simulation Study

IEEE transactions on electron devices, 2019-10, Vol.66 (10), p.4425-4432

2019

Volltextzugriff (PDF)

1 – 25 von 88

Menü

Weitere Dienste

Einstellungen

Nanotube Junctionless FET: Proposal, Design, and Investigation

Controlling L-BTBT and Volume Depletion in Nanowire JLFETs Using Core-Shell Architecture

Junctionless Field-Effect Transistors: Design, Modeling, and Simulation

Realizing Efficient Volume Depletion in SOI Junctionless FETs

Analytical Modeling of Threshold Voltage and Subthreshold Slope for 3-D NAND Flash Memory With a Non-Uniform Doping Profile

Comprehensive Analysis of Gate-Induced Drain Leakage in Emerging FET Architectures: Nanotube FETs Versus Nanowire FETs

Efficient Implementation of Mahalanobis Distance on Ferroelectric FinFET Crossbar for Outlier Detection

Controlling L-BTBT in Emerging Nanotube FETs Using Dual-Material Gate

Analytical Modeling of 3D NAND Flash Cell with a Gaussian Doping Profile

Energy-Efficient Moderate Precision Time-Domain Mixed-Signal Vector-by-Matrix Multiplier Exploiting 1T-1R Arrays

Controlling the Drain Side Tunneling Width to Reduce Ambipolar Current in Tunnel FETs Using Heterodielectric BOX

A Behavioral Compact Model for Static Characteristics of 3D NAND Flash Memory

Physical Insights Into the Nature of Gate-Induced Drain Leakage in Ultrashort Channel Nanowire FETs

Recent trends in hardware security exploiting hybrid CMOS-resistive memory circuits

Parasitic Capacitance Model for Stacked Gate-All-Around Nanosheet FETs

Parasitic Gate Capacitance Model for N-Stack Forksheet FETs

Hybrid CMOS-RRAM True Random Number Generator Exploiting Coupled Entropy Sources

Long Short-Term Memory Implementation Exploiting Passive RRAM Crossbar Array

Diameter Dependence of Leakage Current in Nanowire Junctionless Field Effect Transistors

Insight into Lateral Band-to-Band-Tunneling in Nanowire Junctionless FETs

Spacer Design Guidelines for Nanowire FETs From Gate-Induced Drain Leakage Perspective

Hybrid CMOS-Ferroelectric FET-Based Image Sensor With Tunable Dynamic Range

Hardware Security Primitive Exploiting Intrinsic Variability in Analog Behavior of 3-D NAND Flash Memory Array

Controlling BTBT-Induced Parasitic BJT Action in Junctionless FETs Using a Hybrid Channel

Nanotube Tunneling FET With a Core Source for Ultrasteep Subthreshold Swing: A Simulation Study

Suchergebnisse filtern