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SpaceART SpaceWire Sniffer for Link Monitoring: A Complete Communication Analysis in a Time-Constrained Test Scenario

Sensors (Basel, Switzerland), 2023-02, Vol.23 (3), p.1580

2023

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Design and Implementation of a Configurable Fully Compliant DVB-S2 LDPC Encoder for High Data-Rate Downlink Payload

IEEE access, 2024-01, Vol.12, p.39204-39220

2024

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Secure Elliptic Curve Crypto-Processor for Real-Time IoT Applications

Energies (Basel), 2021-08, Vol.14 (15), p.4676

2021

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Design and Implementation of a DVB-S2 Reconfigurable Datapath BCH Encoder for High Data-Rate Payload Data Telemetry

IEEE access, 2023, Vol.11, p.120281-120291

2023

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Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source

Entropy (Basel, Switzerland), 2022-01, Vol.24 (2), p.139

2022

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Design Methodology and Metrics for Robust and Highly Qualified Security Modules in Trusted Environments

Electronics (Basel), 2023-12, Vol.12 (23), p.4843

2023

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A RISC-V Post Quantum Cryptography Instruction Set Extension for Number Theoretic Transform to Speed-Up CRYSTALS Algorithms

IEEE access, 2021, Vol.9, p.150798-150808

2021

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Review of Methodologies and Metrics for Assessing the Quality of Random Number Generators

Electronics (Basel), 2023-02, Vol.12 (3), p.723

2023

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True Random Number Generator Based on Fibonacci-Galois Ring Oscillators for FPGA

Applied sciences, 2021-04, Vol.11 (8), p.3330

2021

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Design of a Reduced SpaceFibre Interface: An Enabling Technology for Low-Cost Spacecraft High-Speed Data-Handling

Aerospace, 2019-09, Vol.6 (9), p.101

2019

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Next-Generation High-Speed Satellite Interconnect: Disclosing the SpaceFibre Protocol - a System Perspective

1, 2021

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SHINe: Simulator for Satellite on-Board High-Speed Networks Featuring SpaceFibre and SpaceWire Protocols

Aerospace, 2019-04, Vol.6 (4), p.43

2019

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A representative SpaceFibre network evaluation: Features, performances and future trends

Acta astronautica, 2020-11, Vol.176, p.313-323

2020

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Hardware Design of an Advanced-Feature Cryptographic Tile within the European Processor Initiative

IEEE transactions on computers, 2023, p.1-14

2023

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VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative

IEEE transactions on very large scale integration (VLSI) systems, 2022-02, Vol.30 (2), p.177-186

2022

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Clustering Algorithm for a Spaceborne Lightning Imager: Design, Trade-Off, and FPGA Implementation

IEEE journal of selected topics in applied earth observations and remote sensing, 2019-08, Vol.12 (8), p.2781-2791

2019

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The very high-speed SpaceFibre multi-lane CoDec: Implementation and experimental performance evaluation

Acta astronautica, 2021-02, Vol.179, p.462-470

2021

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A serial high-speed satellite communication CODEC: Design and implementation of a SpaceFibre interface

Acta astronautica, 2020-04, Vol.169, p.206-215

2020

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SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative

Microprocessors and microsystems, 2021-11, Vol.87, p.103444, Article 103444

2021

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Satellite High-Speed On-Board Data Handling: From a Wizardlink Equivalent Transceiver To a Full SpaceFibre Interface

2022 IEEE Aerospace Conference (AERO), 2022, p.01-08

2022

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Fault Detection Exploiting Artificial Intelligence in Satellite Systems

The Use of Artificial Intelligence for Space Applications, 2023, Vol.1088, p.151-166

2023

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A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design of System-on-Chip exploiting RISC-V Architecture

2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2021, p.1-6

2021

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Exploiting FPGA Dynamic Partial Reconfiguration for a Soft GPU-based System-on-Chip

2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2023, p.181-184

2023

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SystemVerilog UVM-based Verification Environment for a SpaceFibre Router

2022 International SpaceWire & SpaceFibre Conference (ISC), 2022, p.1-4

2022

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SpaceFibre Network Discovery and Configuration Protocol Development

2022 International SpaceWire & SpaceFibre Conference (ISC), 2022, p.01-08

2022

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SpaceART SpaceWire Sniffer for Link Monitoring: A Complete Communication Analysis in a Time-Constrained Test Scenario

Design and Implementation of a Configurable Fully Compliant DVB-S2 LDPC Encoder for High Data-Rate Downlink Payload

Secure Elliptic Curve Crypto-Processor for Real-Time IoT Applications

Design and Implementation of a DVB-S2 Reconfigurable Datapath BCH Encoder for High Data-Rate Payload Data Telemetry

Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source

Design Methodology and Metrics for Robust and Highly Qualified Security Modules in Trusted Environments

A RISC-V Post Quantum Cryptography Instruction Set Extension for Number Theoretic Transform to Speed-Up CRYSTALS Algorithms

Review of Methodologies and Metrics for Assessing the Quality of Random Number Generators

True Random Number Generator Based on Fibonacci-Galois Ring Oscillators for FPGA

Design of a Reduced SpaceFibre Interface: An Enabling Technology for Low-Cost Spacecraft High-Speed Data-Handling

Next-Generation High-Speed Satellite Interconnect: Disclosing the SpaceFibre Protocol - a System Perspective

SHINe: Simulator for Satellite on-Board High-Speed Networks Featuring SpaceFibre and SpaceWire Protocols

A representative SpaceFibre network evaluation: Features, performances and future trends

Hardware Design of an Advanced-Feature Cryptographic Tile within the European Processor Initiative

VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative

Clustering Algorithm for a Spaceborne Lightning Imager: Design, Trade-Off, and FPGA Implementation

The very high-speed SpaceFibre multi-lane CoDec: Implementation and experimental performance evaluation

A serial high-speed satellite communication CODEC: Design and implementation of a SpaceFibre interface

SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative

Satellite High-Speed On-Board Data Handling: From a Wizardlink Equivalent Transceiver To a Full SpaceFibre Interface

Fault Detection Exploiting Artificial Intelligence in Satellite Systems

A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design of System-on-Chip exploiting RISC-V Architecture

Exploiting FPGA Dynamic Partial Reconfiguration for a Soft GPU-based System-on-Chip

SystemVerilog UVM-based Verification Environment for a SpaceFibre Router

SpaceFibre Network Discovery and Configuration Protocol Development

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