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System Design Framework and Methodology for Xilinx Virtex FPGA Configuration Scrubbers

IEEE transactions on nuclear science, 2014-02, Vol.61 (1), p.619-629

2014

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Conformational impact of aliphatic side chains in local anaesthetics: benzocaine, butamben and isobutamben

Chemical communications (Cambridge, England), 2020-06, Vol.56 (45), p.694-697

2020

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Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers

IEEE transactions on nuclear science, 2013-02, Vol.60 (1), p.376-385

2013

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On the hardware-software partitioning problem: System modeling and partitioning techniques

ACM transactions on design automation of electronic systems, 2003-07, Vol.8 (3), p.269-297

2003

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A Dual-Layer Fault Manager for systems based on Xilinx Virtex FPGAs

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015, p.72-75

2015

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Implementing FFT-based digital channelized receivers on FPGA platforms

IEEE transactions on aerospace and electronic systems, 2008-10, Vol.44 (4), p.1567-1585

2008

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A Nanowatt Smart Temperature Sensor for Dynamic Thermal Management

IEEE sensors journal, 2008-12, Vol.8 (12), p.2036-2043

2008

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Ratio-Based Temperature-Sensing Technique Hardened Against Nanometer Process Variations

IEEE sensors journal, 2013-02, Vol.13 (2), p.442-443

2013

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Digital channelised receivers on FPGAs platforms

IEEE International Radar Conference, 2005, 2005, p.816-821

2005

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Cycle-accurate configuration layer model for Xilinx Virtex FPGAs

2011 12th European Conference on Radiation and Its Effects on Components and Systems, 2011, p.182-185

2011

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Light-Weight On-Chip Monitoring Network for Dynamic Adaptation and Calibration

IEEE sensors journal, 2012-06, Vol.12 (6), p.1736-1745

2012

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An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling

2003 Design, Automation and Test in Europe Conference and Exhibition, 2003, Vol.1, p.10428-433

2003

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Constraint-driven system partitioning

Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe; 27-30 Mar. 2000, 2000, p.411-416

2000

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Experimental methodology for power characterization of FPGAs

2008 15th IEEE International Conference on Electronics, Circuits and Systems, 2008, p.582-585

2008

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Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors

2007 IEEE International Symposium on Circuits and Systems (ISCAS), 2007, p.121-124

2007

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A low-power architecture for maximum a posteriori decoding

Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002, 2002, Vol.1, p.47-51 vol.1

2002

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FPGA Gaussian random number generator based on quintic hermite interpolation inversion

2007 50th Midwest Symposium on Circuits and Systems, 2007, p.871-874

2007

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Design of a pipelined hardware architecture for real-time neural network computations

The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002, 2002, Vol.1, p.I-419

2002

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Power-Aware Compilation for Register File Energy Reduction

International journal of parallel programming, 2003-12, Vol.31 (6), p.451-467

2003

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Energy aware register file implementation through instruction predecode

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003, 2003, p.86-96

2003

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Leakage-based On-Chip Thermal Sensor for CMOS Technology

2007 IEEE International Symposium on Circuits and Systems (ISCAS), 2007, p.3327-3330

2007

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Optimal loop-unrolling mechanisms and architectural extensions for an energy-efficient design of shared register files in MPSoCs

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05), 2005, p.7 pp.

2005

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Temperature sensor placement including routing overhead and sampling inaccuracies

2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012, p.69-72

2012

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Applying the propose&revise strategy to the hardware-software partitioning problem

Lecture Notes In Computer Science; Vol. 1415: Proceedings of the 11th international conference on Industrial and engineering applications of artificial intelligence and expert systems: methodology and tools in knowledge-based systems; 01-04 June 1998, 2005, p.169-179

2005

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On-chip Monitoring: A Light-Weight Interconnection Network Approach

2011 14th Euromicro Conference on Digital System Design, 2011, p.619-625

2011

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System Design Framework and Methodology for Xilinx Virtex FPGA Configuration Scrubbers

Conformational impact of aliphatic side chains in local anaesthetics: benzocaine, butamben and isobutamben

Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers

On the hardware-software partitioning problem: System modeling and partitioning techniques

A Dual-Layer Fault Manager for systems based on Xilinx Virtex FPGAs

Implementing FFT-based digital channelized receivers on FPGA platforms

A Nanowatt Smart Temperature Sensor for Dynamic Thermal Management

Ratio-Based Temperature-Sensing Technique Hardened Against Nanometer Process Variations

Digital channelised receivers on FPGAs platforms

Cycle-accurate configuration layer model for Xilinx Virtex FPGAs

Light-Weight On-Chip Monitoring Network for Dynamic Adaptation and Calibration

An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling

Constraint-driven system partitioning

Experimental methodology for power characterization of FPGAs

Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors

A low-power architecture for maximum a posteriori decoding

FPGA Gaussian random number generator based on quintic hermite interpolation inversion

Design of a pipelined hardware architecture for real-time neural network computations

Power-Aware Compilation for Register File Energy Reduction

Energy aware register file implementation through instruction predecode

Leakage-based On-Chip Thermal Sensor for CMOS Technology

Optimal loop-unrolling mechanisms and architectural extensions for an energy-efficient design of shared register files in MPSoCs

Temperature sensor placement including routing overhead and sampling inaccuracies

Applying the propose&revise strategy to the hardware-software partitioning problem

On-chip Monitoring: A Light-Weight Interconnection Network Approach

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