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A compact model for NBTI degradation and recovery under use-profile variations and its application to aging analysis of digital integrated circuits
Microelectronics and reliability, 2014-06, Vol.54 (6-7), p.1083-1089
2014
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Design & verification of automotive SoC firmware
2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, p.1-6
2015
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Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience
Microelectronics and reliability, 2014-06, Vol.54 (6-7), p.1066-1074
2014
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A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience
IEEE MICRO, 2013-07, Vol.33 (4), p.46-55
2013
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Application-aware cross-layer reliability analysis and optimization
Information technology (Munich, Germany), 2015-06, Vol.57 (3), p.159-169
2015
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Connecting different worlds - Technology abstraction for reliability-aware design and Test
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, p.1-8
2014
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Fault Injection for Test-Driven Development of Robust SoC Firmware
ACM transactions on embedded computing systems, 2018-01, Vol.17 (1), p.1-26
2018
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Workload- and Instruction-Aware Timing Analysis: The missing Link between Technology and System-level Resilience
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 2014, p.1-6
2014
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A compact model for NBTI degradation and recovery under use-profile variations and its application to aging analysis of digital integrated circuits : RELIABILITY AND VARIABILITY OF DEVICES FOR CIRCUITS AND SYSTEMS
Microelectronics and reliability, 2014, Vol.54 (6-7), p.1083-1089
2014
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Technology-aware system failure analysis in the presence of soft errors by Mixture Importance Sampling
2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2013, p.118-124
2013
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Goldilocks failures: Not too soft, not too hard
2012 IEEE International Reliability Physics Symposium (IRPS), 2012, p.2F.1.1-2F.1.5
2012
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Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience : RELIABILITY AND VARIABILITY OF DEVICES FOR CIRCUITS AND SYSTEMS
Microelectronics and reliability, 2014, Vol.54 (6-7), p.1066-1074
2014
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Reliability analysis of digital circuits considering intrinsic noise
2011 3rd Asia Symposium on Quality Electronic Design (ASQED), 2011, p.167-173
2011
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Program-aware circuit level timing analysis
2011 International Symposium on Integrated Circuits, 2011, p.102-105
2011
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Fast and waveform independent characterization of current source models
2009 IEEE Behavioral Modeling and Simulation Workshop, 2009, p.90-95
2009
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Characterization and implementation of nonlinear logic cell models for analog circuit simulation
Proceedings of the 2009 12th International Symposium on Integrated Circuits, 2009, p.97-100
2009
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