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SCALEDEEP: A scalable compute architecture for learning and evaluating deep networks

2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), 2017, p.13-26

2017

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Accelerating Sequential Applications on CMPs Using Core Spilling

IEEE transactions on parallel and distributed systems, 2007-08, Vol.18 (8), p.1094-1107

2007

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An automated design flow for 3D microarchitecture evaluation

Proceedings of the 2006 Asia and South Pacific Design Automation Conference, 2006, p.384-389

2006

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Timing-driven maze routing

IEEE transactions on computer-aided design of integrated circuits and systems, 2000-02, Vol.19 (2), p.234-241

2000

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Microarchitecture evaluation with physical planning

Annual ACM IEEE Design Automation Conference: Proceedings of the 40th conference on Design automation; 02-06 June 2003, 2003, p.32-35

2003

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A fast algorithm for context-aware buffer insertion

Annual ACM IEEE Design Automation Conference: Proceedings of the 37th conference on Design automation; 05-09 June 2000, 2000, p.368-373

2000

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A fast algorithm for context-aware buffer insertion

ACM transactions on design automation of electronic systems, 2002-01, Vol.7 (1), p.173-188

2002

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ScaleDeep: A Scalable Compute Architecture for Learning and Evaluating Deep Networks

Computer architecture news, 2017-09, Vol.45 (2), p.13-26

2017

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Instruction set extension with shadow registers for configurable processors

International Symposium on Field Programmable Gate Arrays: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays; 20-22 Feb. 2005, 2005, p.99-106

2005

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An automated design flow for 3D microarchitecture evaluation

Asia and South Pacific Conference on Design Automation, 2006, 2006, p.6 pp.

2006

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Understanding the energy efficiency of SMT and CMP with multiclustering

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, 2005, p.48-53

2005

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Microarchitecture evaluation with floorplanning and interconnect pipelining

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005, 2005, Vol.1, p.I/8-I15 Vol. 1

2005

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Timing driven maze routing

International Symposium on Physical Design: Proceedings of the 1999 international symposium on Physical design; 12-14 Apr. 1999, 1999, p.208-213

1999

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Microarchitecture evaluation with floorplanning and interconnect pipelining

Proceedings of the 2005 Asia and South Pacific Design Automation Conference, 2005, p.8-15

2005

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Placement-driven technology mapping for LUT-based FPGAs

International Symposium on Field Programmable Gate Arrays: Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays; 23-25 Feb. 2003, 2003, p.121-126

2003

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