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Deep Learning for Computational Problems in Hardware Security: Modeling Attacks on Strong Physically Unclonable Function Circuits

1, 2022

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A Computationally Efficient Tensor Regression Network-Based Modeling Attack on XOR Arbiter PUF and Its Variants

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-06, Vol.40 (6), p.1197-1206

2021

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IEEE_Xplore

Hardware security: design, threats, and safeguards

2014

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A PUF-Based Secure Communication Protocol for IoT

ACM transactions on embedded computing systems, 2017-08, Vol.16 (3), p.1-25

2017

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Digital Image Forensics: Theory and Implementation

1st ed. 2020., 2019

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High Performance Integer Arithmetic Circuit Design on FPGA: Architecture, Implementation and Design Automation

2016, 2015

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Novel Hardware Trojan Attack on Activation Parameters of FPGA-Based DNN Accelerators

IEEE embedded systems letters, 2022-09, Vol.14 (3), p.131-134

2022

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IEEE_Xplore

Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis

IEEE transactions on computers, 2013-11, Vol.62 (11), p.2183-2195

2013

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IEEE_Xplore

Improved Test Pattern Generation for Hardware Trojan Detection Using Genetic Algorithm and Boolean Satisfiability

Cryptographic Hardware and Embedded Systems -- CHES 2015, p.577-596

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Histogram-bin-shifting-based reversible watermarking for colour images

IET image processing, 2013-03, Vol.7 (2), p.99-110

2013

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Artificial Intelligence and Deep Learning for Computer Network: Management and Analysis

1, 2023

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A Case of Lightweight PUF Constructions: Cryptanalysis and Machine Learning Attacks

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-08, Vol.34 (8), p.1334-1343

2015

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IEEE_Xplore

Reversible Digital Watermarking: Theory and Practices

Ruchira Naskar, Rajat Subhra Chakraborty

1, 2014

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MERO: A Statistical Approach for Hardware Trojan Detection

Cryptographic Hardware and Embedded Systems - CHES 2009, p.396-410

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Security, Privacy, and Applied Cryptography Engineering: 5th International Conference, SPACE 2015, Jaipur, India, October 3-7, 2015, Proceedings

1st ed. 2015, 2015

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Binary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slices

IET computers & digital techniques, 2021-03, Vol.15 (2), p.112-124

2021

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Low Cost Memristor Associative Memory Design for Full and Partial Matching Applications

IEEE transactions on nanotechnology, 2016-05, Vol.15 (3), p.527-538

2016

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IEEE_Xplore

A generalized tamper localization approach for reversible watermarking algorithms

ACM transactions on multimedia computing communications and applications, 2013-06, Vol.9 (3), p.1-22

2013

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Security and Fault Tolerance in Internet of Things

1st ed. 2019., 2019

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Self-referencing: A Scalable Side-Channel Approach for Hardware Trojan Detection

Cryptographic Hardware and Embedded Systems, CHES 2010, p.173-187

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Toward Optimal Prediction Error Expansion-Based Reversible Image Watermarking

IEEE transactions on circuits and systems for video technology, 2020-08, Vol.30 (8), p.2377-2390

2020

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IEEE_Xplore

Reversible Digital Watermarking: Theory and Practices

1st edition., 2022

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Attacks on Recent DNN IP Protection Techniques and Their Mitigation

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-11, Vol.42 (11), p.1-1

2023

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IEEE_Xplore

Correlation Integral-Based Intrinsic Dimension: A Deep-Learning-Assisted Empirical Metric to Estimate the Robustness of Physically Unclonable Functions to Modeling Attacks

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-10, Vol.41 (10), p.3216-3227

2022

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IEEE_Xplore

Revisiting the Security of LPN Based RFID Authentication Protocol and Potential Exploits in Hardware Implementations

Security, Privacy, and Applied Cryptography Engineering, 2019, Vol.11947, p.214-230

2019

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Deep Learning for Computational Problems in Hardware Security: Modeling Attacks on Strong Physically Unclonable Function Circuits

A Computationally Efficient Tensor Regression Network-Based Modeling Attack on XOR Arbiter PUF and Its Variants

Hardware security: design, threats, and safeguards

A PUF-Based Secure Communication Protocol for IoT

Digital Image Forensics: Theory and Implementation

High Performance Integer Arithmetic Circuit Design on FPGA: Architecture, Implementation and Design Automation

Novel Hardware Trojan Attack on Activation Parameters of FPGA-Based DNN Accelerators

Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis

Improved Test Pattern Generation for Hardware Trojan Detection Using Genetic Algorithm and Boolean Satisfiability

Histogram-bin-shifting-based reversible watermarking for colour images

Artificial Intelligence and Deep Learning for Computer Network: Management and Analysis

A Case of Lightweight PUF Constructions: Cryptanalysis and Machine Learning Attacks

Reversible Digital Watermarking: Theory and Practices

MERO: A Statistical Approach for Hardware Trojan Detection

Security, Privacy, and Applied Cryptography Engineering: 5th International Conference, SPACE 2015, Jaipur, India, October 3-7, 2015, Proceedings

Binary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slices

Low Cost Memristor Associative Memory Design for Full and Partial Matching Applications

A generalized tamper localization approach for reversible watermarking algorithms

Security and Fault Tolerance in Internet of Things

Self-referencing: A Scalable Side-Channel Approach for Hardware Trojan Detection

Toward Optimal Prediction Error Expansion-Based Reversible Image Watermarking

Reversible Digital Watermarking: Theory and Practices

Attacks on Recent DNN IP Protection Techniques and Their Mitigation

Correlation Integral-Based Intrinsic Dimension: A Deep-Learning-Assisted Empirical Metric to Estimate the Robustness of Physically Unclonable Functions to Modeling Attacks

Revisiting the Security of LPN Based RFID Authentication Protocol and Potential Exploits in Hardware Implementations

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