UB Paderborn / Katalog / Suche / in CDI

1 – 25 von 29

Sortiert nach

SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing

IEEE transactions on circuits and systems. I, Regular papers, 2020-07, Vol.67 (7), p.2317-2330

2020

Link zum Volltext
Volltext

A Lightweight FPGA Compatible Weak-PUF Primitive Based on XOR Gates

IEEE transactions on circuits and systems. II, Express briefs, 2022-06, Vol.69 (6), p.2972-2976

2022

Link zum Volltext
Volltext

A Novel Ultra-Compact FPGA PUF: The DD-PUF

Cryptography, 2021-09, Vol.5 (3), p.23

2021

Link zum Volltext

Verfügbarkeit prüfen

Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks

IEEE transactions on very large scale integration (VLSI) systems, 2018-07, Vol.26 (7), p.1368-1376

2018

Link zum Volltext
Volltext

A Monostable Physically Unclonable Function Based on Improved RCCMs with 0–1.56% Native Bit Instability at 0.6–1.2 V and 0–75 °C

Electronics (Basel), 2023-02, Vol.12 (3), p.755

2023

Link zum Volltext

Verfügbarkeit prüfen

SC-DDPL as a Countermeasure against Static Power Side-Channel Attacks

Cryptography, 2021-09, Vol.5 (3), p.16

2021

Link zum Volltext

Verfügbarkeit prüfen

Side-channel analysis of a learning parity with physical noise processor

Journal of cryptographic engineering, 2021-06, Vol.11 (2), p.171-179

2021

Link zum Volltext

Verfügbarkeit prüfen

TEL Logic Style as a Countermeasure Against Side-Channel Attacks: Secure Cells Library in 65nm CMOS and Experimental Results

IEEE transactions on circuits and systems. I, Regular papers, 2018-11, Vol.65 (11), p.3874-3884

2018

Link zum Volltext
Volltext

A Novel Ultra-Compact FPGA-Compatible TRNG Architecture Exploiting Latched Ring Oscillators

IEEE transactions on circuits and systems. II, Express briefs, 2022-03, Vol.69 (3), p.1672-1676

2022

Link zum Volltext
Volltext

High-Throughput FPGA-Compatible TRNG Architecture Exploiting Multistimuli Metastable Cells

IEEE transactions on circuits and systems. I, Regular papers, 2022-12, Vol.69 (12), p.4886-4897

2022

Link zum Volltext
Volltext

Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies

IEEE transactions on very large scale integration (VLSI) systems, 2017-12, Vol.25 (12), p.3509-3520

2017

Link zum Volltext
Volltext

Ask Less, Get More: Side-Channel Signal Hiding, Revisited

IEEE transactions on circuits and systems. I, Regular papers, 2020-12, Vol.67 (12), p.4904-4917

2020

Link zum Volltext
Volltext

An In-Depth Evaluation of Externally Amplified Coupling (EAC) Attacks-A Concrete Threat for Masked Cryptographic Implementations

IEEE transactions on circuits and systems. I, Regular papers, 2023-02, Vol.70 (2), p.783-796

2023

Link zum Volltext
Volltext

Tight-ES-TRNG: Improved Construction and Robustness Analysis

SN computer science, 2022-07, Vol.3 (4), p.321, Article 321

2022

Link zum Volltext

Verfügbarkeit prüfen

Univariate Power Analysis Attacks Exploiting Static Dissipation of Nanometer CMOS VLSI Circuits for Cryptographic Applications

IEEE transactions on emerging topics in computing, 2017-07, Vol.5 (3), p.329-339

2017

Link zum Volltext
Volltext

Beyond algorithmic noise or how to shuffle parallel implementations?

International journal of circuit theory and applications, 2020-05, Vol.48 (5), p.674-695

2020

Link zum Volltext

Verfügbarkeit prüfen

Template attacks exploiting static power and application to CMOS lightweight crypto‐hardware

International journal of circuit theory and applications, 2017-02, Vol.45 (2), p.229-241

2017

Link zum Volltext

Verfügbarkeit prüfen

Towards a Better Understanding of Side-Channel Analysis Measurements Setups

Smart Card Research and Advanced Applications, p.64-79

Link zum Volltext

Verfügbarkeit prüfen

Multivariate Analysis Exploiting Static Power on Nanoscale CMOS Circuits for Cryptographic Applications

Progress in Cryptology - AFRICACRYPT 2017, p.79-94

Link zum Volltext

Verfügbarkeit prüfen

Post-Quantum Cryptography: Challenges and Opportunities for Robust and Secure HW Design

2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2021, p.1-6

2021

Link zum Volltext
Volltext

Mode-Level vs. Implementation-Level Physical Security in Symmetric Cryptography: A Practical Guide Through the Leakage-Resistance Jungle

Advances in Cryptology – CRYPTO 2020, p.369-400

Link zum Volltext

Verfügbarkeit prüfen

A Systematic Appraisal of Side Channel Evaluation Strategies

Security Standardisation Research, 2020, Vol.12529, p.46-66

2020

Link zum Volltext

Verfügbarkeit prüfen

Implementation of the PRESENT-80 block cipher and analysis of its vulnerability to Side Channel Attacks Exploiting Static Power

2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems, 2016, p.211-216

2016

Link zum Volltext

Verfügbarkeit prüfen

VHDL implementation of FWL RLS algorithm

2017 European Conference on Circuit Theory and Design (ECCTD), 2017, p.1-4

2017

Link zum Volltext
Volltext

A Novel Very Low Voltage Topology to implement MCML XOR Gates

2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), 2018, p.157-160

2018

Link zum Volltext

Verfügbarkeit prüfen

1 – 25 von 29

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(21)
Mit Volltextzugriff
(25)

Publikationsform

Sprache

Englisch
(29)
Japanisch
(3)

Erscheinungsjahr

n.n

Thema

Science & Technology
(17)
Technology
(17)
Cryptography
(13)
Logic Gates
(12)
Engineering
(11)
Engineering, Electrical & Electronic
(11)
Computer Science
(10)
Cmos
(9)
Power Consumption
(8)
Power Demand
(8)
Field Programmable Gate Arrays
(7)
Computer Architecture
(6)
Computer Science, Theory & Methods
(6)
Security
(6)
Algorithms
(5)
Hardware Security
(5)
Nanometer Cmos
(5)
Transistors
(5)
Clocks
(4)
Cmos Technology
(4)

15 weitere anzeigen...

Weniger anzeigen...

Menü

Weitere Dienste

Einstellungen

SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing

A Lightweight FPGA Compatible Weak-PUF Primitive Based on XOR Gates

A Novel Ultra-Compact FPGA PUF: The DD-PUF

Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks

A Monostable Physically Unclonable Function Based on Improved RCCMs with 0–1.56% Native Bit Instability at 0.6–1.2 V and 0–75 °C

SC-DDPL as a Countermeasure against Static Power Side-Channel Attacks

Side-channel analysis of a learning parity with physical noise processor

TEL Logic Style as a Countermeasure Against Side-Channel Attacks: Secure Cells Library in 65nm CMOS and Experimental Results

A Novel Ultra-Compact FPGA-Compatible TRNG Architecture Exploiting Latched Ring Oscillators

High-Throughput FPGA-Compatible TRNG Architecture Exploiting Multistimuli Metastable Cells

Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies

Ask Less, Get More: Side-Channel Signal Hiding, Revisited

An In-Depth Evaluation of Externally Amplified Coupling (EAC) Attacks-A Concrete Threat for Masked Cryptographic Implementations

Tight-ES-TRNG: Improved Construction and Robustness Analysis

Univariate Power Analysis Attacks Exploiting Static Dissipation of Nanometer CMOS VLSI Circuits for Cryptographic Applications

Beyond algorithmic noise or how to shuffle parallel implementations?

Template attacks exploiting static power and application to CMOS lightweight crypto‐hardware

Towards a Better Understanding of Side-Channel Analysis Measurements Setups

Multivariate Analysis Exploiting Static Power on Nanoscale CMOS Circuits for Cryptographic Applications

Post-Quantum Cryptography: Challenges and Opportunities for Robust and Secure HW Design

Mode-Level vs. Implementation-Level Physical Security in Symmetric Cryptography: A Practical Guide Through the Leakage-Resistance Jungle

A Systematic Appraisal of Side Channel Evaluation Strategies

Implementation of the PRESENT-80 block cipher and analysis of its vulnerability to Side Channel Attacks Exploiting Static Power

VHDL implementation of FWL RLS algorithm

A Novel Very Low Voltage Topology to implement MCML XOR Gates

Suchergebnisse filtern