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HIRE-SNN: Harnessing the Inherent Robustness of Energy-Efficient Deep Spiking Neural Networks by Training with Crafted Input Noise

2021 IEEE/CVF International Conference on Computer Vision (ICCV), 2021, p.5189-5198

2021

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Can Deep Neural Networks be Converted to Ultra Low-Latency Spiking Neural Networks?

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022, p.718-723

2022

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ACE-SNN: Algorithm-Hardware Co-design of Energy-Efficient & Low-Latency Deep Spiking Neural Networks for 3D Image Recognition

Frontiers in neuroscience, 2022-04, Vol.16, p.815258

2022

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Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs Using Graph-Based Retiming

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-04, Vol.41 (4), p.979-992

2022

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On the Security of Sequential Logic Locking Against Oracle-Guided Attacks

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-11, Vol.42 (11), p.1-1

2023

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A processing-in-pixel-in-memory paradigm for resource-constrained TinyML applications

Scientific reports, 2022-08, Vol.12 (1), p.14396-14396, Article 14396

2022

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Metastability in Superconducting Single Flux Quantum (SFQ) Logic

IEEE transactions on circuits and systems. I, Regular papers, 2021-05, Vol.68 (5), p.1990-2002

2021

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SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol

IEEE transactions on circuits and systems. I, Regular papers, 2020-05, Vol.67 (5), p.1667-1677

2020

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A Robust and Self-Adaptive Clocking Technique for SFQ Circuits

IEEE transactions on applied superconductivity, 2018-10, Vol.28 (7), p.1-11

2018

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Programming memristor arrays with arbitrarily high precision for analog computing

Science (American Association for the Advancement of Science), 2024-02, Vol.383 (6685), p.903-910

2024

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BMPQ: Bit-Gradient Sensitivity-Driven Mixed-Precision Quantization of DNNs from Scratch

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022, p.588-591

2022

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Optimizing (HC)[Formula Omitted] LC, A Robust Clock Distribution Network For SFQ Circuits

IEEE transactions on applied superconductivity, 2020-01, Vol.30 (1), p.1

2020

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SystemVerilog Modeling of SFQ and AQFP Circuits

IEEE transactions on applied superconductivity, 2020-03, Vol.30 (2), p.1-13

2020

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GF-Flush: A GF(2) Algebraic Attack on Dynamically Secured Scan Chains

2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2021, p.1-6

2021

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Single Flux Quantum (SFQ) First-in-First-Out (FIFO) Synchronizers: New Designs and Paradigms

IEEE transactions on applied superconductivity, 2020-10, Vol.30 (7), p.1-8

2020

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Neuromorphic-P2M: processing-in-pixel-in-memory paradigm for neuromorphic image sensors

Frontiers in neuroinformatics, 2023-05, Vol.17, p.1144301-1144301

2023

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Pre-Defined Sparse Neural Networks With Hardware Acceleration

IEEE journal on emerging and selected topics in circuits and systems, 2019-06, Vol.9 (2), p.332-345

2019

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TriLock: IC Protection with Tunable Corruptibility and Resilience to SAT and Removal Attacks

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022, p.1329-1334

2022

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Automatic Retiming of Two-Phase Latch-Based Resilient Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-07, Vol.38 (7), p.1305-1316

2019

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Yield modelling and analysis of bundled data and ring-oscillator based designs

IET computers & digital techniques, 2019-05, Vol.13 (3), p.262-272

2019

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Area-Efficient Asynchronous Multilevel Single-Track Pipeline Template

IEEE transactions on very large scale integration (VLSI) systems, 2014-04, Vol.22 (4), p.838-849

2014

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NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization

IEEE transactions on circuits and systems. I, Regular papers, 2018-06, Vol.65 (6), p.1981-1993

2018

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Saving power by converting flip-flop to 3-phase latch-based designs

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, p.574-579

2020

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Deep-n-Cheap: An Automated Efficient and Extensible Search Framework for Cost-Effective Deep Learning

SN computer science, 2021-07, Vol.2 (4), p.265, Article 265

2021

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High performance asynchronous design using single-track full-buffer standard cells

IEEE journal of solid-state circuits, 2006-06, Vol.41 (6), p.1444-1454

2006

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HIRE-SNN: Harnessing the Inherent Robustness of Energy-Efficient Deep Spiking Neural Networks by Training with Crafted Input Noise

Can Deep Neural Networks be Converted to Ultra Low-Latency Spiking Neural Networks?

ACE-SNN: Algorithm-Hardware Co-design of Energy-Efficient & Low-Latency Deep Spiking Neural Networks for 3D Image Recognition

Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs Using Graph-Based Retiming

On the Security of Sequential Logic Locking Against Oracle-Guided Attacks

A processing-in-pixel-in-memory paradigm for resource-constrained TinyML applications

Metastability in Superconducting Single Flux Quantum (SFQ) Logic

SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol

A Robust and Self-Adaptive Clocking Technique for SFQ Circuits

Programming memristor arrays with arbitrarily high precision for analog computing

BMPQ: Bit-Gradient Sensitivity-Driven Mixed-Precision Quantization of DNNs from Scratch

Optimizing (HC)[Formula Omitted] LC, A Robust Clock Distribution Network For SFQ Circuits

SystemVerilog Modeling of SFQ and AQFP Circuits

GF-Flush: A GF(2) Algebraic Attack on Dynamically Secured Scan Chains

Single Flux Quantum (SFQ) First-in-First-Out (FIFO) Synchronizers: New Designs and Paradigms

Neuromorphic-P2M: processing-in-pixel-in-memory paradigm for neuromorphic image sensors

Pre-Defined Sparse Neural Networks With Hardware Acceleration

TriLock: IC Protection with Tunable Corruptibility and Resilience to SAT and Removal Attacks

Automatic Retiming of Two-Phase Latch-Based Resilient Circuits

Yield modelling and analysis of bundled data and ring-oscillator based designs

Area-Efficient Asynchronous Multilevel Single-Track Pipeline Template

NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization

Saving power by converting flip-flop to 3-phase latch-based designs

Deep-n-Cheap: An Automated Efficient and Extensible Search Framework for Cost-Effective Deep Learning

High performance asynchronous design using single-track full-buffer standard cells

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