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A 3nm GAAFET Analog Assisted Digital LDO with High Current Density for Dynamic Voltage Scaling Mobile Applications

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.190-191

2022

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Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

IEEE access, 2021, Vol.9, p.46573-46588

2021

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A 0.3V-VIN, 0.015ps-FoM Fully Integrated Analog-Assisted Digital LDO with Dual-Negative Gate Control and Adaptive Transient Recovery Path

IEEE transactions on power electronics, 2023-01, p.1-5

2023

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A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response

IEEE journal of solid-state circuits, 2020-04, Vol.55 (4), p.977-987

2020

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A Dynamically High-Impedance Charge-Pump-Based LDO With Digital-LDO-Like Properties Achieving a Sub-4-fs FoM

IEEE journal of solid-state circuits, 2020-03, Vol.55 (3), p.719-730

2020

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A DVS-Enabled Distributed Digital LDO Providing Rapid Uniform Power Grid and Ripple Reduction Achieving 20.1-ps FOM in 28 nm CMOS

IEEE transactions on circuits and systems. I, Regular papers, 2024-07, p.1-10

2024

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An Autonomous Energy Harvesting Power Management Unit With Digital Regulation for IoT Applications

IEEE journal of solid-state circuits, 2016-06, Vol.51 (6), p.1457-1474

2016

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A 96.1% Efficiency Single-Inductor Multiple-Output (SIMO) Buck Converter With 2.1-A/ns Transient Speed and 2.2-A Maximum Current Capacity

IEEE journal of solid-state circuits, 2024-08, Vol.59 (8), p.2545-2556

2024

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A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits

IEEE journal of solid-state circuits, 2014-11, Vol.49 (11), p.2684-2693

2014

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Architectural Advancement of Digital Low-Dropout Regulators

IEEE access, 2020-01, Vol.8, p.1-1

2020

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A Capacitor-Less Ripple-Less Hybrid LDO With Exponential Ratio Array and 4000x Load Current Range

IEEE transactions on circuits and systems. II, Express briefs, 2019-01, Vol.66 (1), p.36-40

2019

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A Fast Transient Response Hybrid LDO With Highly Accurate DC Voltage Using Countable Bidirectional Binary Search and Soft Swap Switching

IEEE transactions on circuits and systems. II, Express briefs, 2020-12, Vol.67 (12), p.3272-3276

2020

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Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator

IEEE journal of solid-state circuits, 2016-01, Vol.51 (1), p.18-30

2016

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An Output-Capacitor-Free NMOS Digital LDO Using Gate Driving Strength Modulation and Droop Detector

IEEE transactions on circuits and systems. I, Regular papers, 2023-12, Vol.70 (12), p.1-11

2023

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A CMOS standard-cell based fully-synthesizable low-dropout regulator for ultra-low power applications

International journal of electronics and communications, 2021-11, Vol.141, p.153958, Article 153958

2021

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A Single-Controller-Four-Output Digital LDO With Priority-Time-Multiplexing Scheme and Clamping Loops in 65-nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2024-03, Vol.71 (3), p.1-1

2024

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A 100 MHz, 0.8-to-1.1 V, 170 mA Digital LDO With 8-Cycles Mean Settling Time and 9-Bit Regulating Resolution in 180-nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2020-09, Vol.67 (9), p.1664-1668

2020

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A Distributed Power Delivery Grid Based on Analog-Assisted Digital LDOs With Cooperative Regulation and IR-Drop Reduction

IEEE transactions on circuits and systems. I, Regular papers, 2020-08, Vol.67 (8), p.2859-2871

2020

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A Tri-loop Fast-transient Digital LDO with Adaptive-gain Control and Fine-loop Freezer

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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Digital LDO regulator with analogue-assisted loop using source follower

Electronics letters, 2020-08, Vol.56 (16), p.801-803

2020

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A Highly Synthesizable 0.5-to-1.0-V Digital Low-Dropout Regulator With Adaptive Clocking and Incremental Regulation Scheme

IEEE transactions on circuits and systems. II, Express briefs, 2020-10, Vol.67 (10), p.2174-2178

2020

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An Analog-Assisted Digital LDO With Dynamic-Biasing Asynchronous Comparator

IEEE access, 2022, Vol.10, p.56996-57002

2022

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A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement

IEEE journal of solid-state circuits, 2013-04, Vol.48 (4), p.1018-1030

2013

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Flash ADC-based digital LDO with non-linear decoder and exponential-ratio array

Electronics letters, 2019-05, Vol.55 (10), p.585-587

2019

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A Current Efficient 10mA Analog-Assisted Digital Low Dropout Regulator with Dynamic Clock Frequency in 65nm CMOS

2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, p.1-5

2020

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A 3nm GAAFET Analog Assisted Digital LDO with High Current Density for Dynamic Voltage Scaling Mobile Applications

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

A 0.3V-VIN, 0.015ps-FoM Fully Integrated Analog-Assisted Digital LDO with Dual-Negative Gate Control and Adaptive Transient Recovery Path

A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response

A Dynamically High-Impedance Charge-Pump-Based LDO With Digital-LDO-Like Properties Achieving a Sub-4-fs FoM

A DVS-Enabled Distributed Digital LDO Providing Rapid Uniform Power Grid and Ripple Reduction Achieving 20.1-ps FOM in 28 nm CMOS

An Autonomous Energy Harvesting Power Management Unit With Digital Regulation for IoT Applications

A 96.1% Efficiency Single-Inductor Multiple-Output (SIMO) Buck Converter With 2.1-A/ns Transient Speed and 2.2-A Maximum Current Capacity

A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits

Architectural Advancement of Digital Low-Dropout Regulators

A Capacitor-Less Ripple-Less Hybrid LDO With Exponential Ratio Array and 4000x Load Current Range

A Fast Transient Response Hybrid LDO With Highly Accurate DC Voltage Using Countable Bidirectional Binary Search and Soft Swap Switching

Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator

An Output-Capacitor-Free NMOS Digital LDO Using Gate Driving Strength Modulation and Droop Detector

A CMOS standard-cell based fully-synthesizable low-dropout regulator for ultra-low power applications

A Single-Controller-Four-Output Digital LDO With Priority-Time-Multiplexing Scheme and Clamping Loops in 65-nm CMOS

A 100 MHz, 0.8-to-1.1 V, 170 mA Digital LDO With 8-Cycles Mean Settling Time and 9-Bit Regulating Resolution in 180-nm CMOS

A Distributed Power Delivery Grid Based on Analog-Assisted Digital LDOs With Cooperative Regulation and IR-Drop Reduction

A Tri-loop Fast-transient Digital LDO with Adaptive-gain Control and Fine-loop Freezer

Digital LDO regulator with analogue-assisted loop using source follower

A Highly Synthesizable 0.5-to-1.0-V Digital Low-Dropout Regulator With Adaptive Clocking and Incremental Regulation Scheme

An Analog-Assisted Digital LDO With Dynamic-Biasing Asynchronous Comparator

A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement

Flash ADC-based digital LDO with non-linear decoder and exponential-ratio array

A Current Efficient 10mA Analog-Assisted Digital Low Dropout Regulator with Dynamic Clock Frequency in 65nm CMOS

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