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An algorithm for obstacle-avoiding clock routing tree construction with multiple TSVs on a 3D IC

Chronic diseases and translational medicine, 2019-03, Vol.13 (2), p.102-109

2019

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Low Power Techniques for Digital System Design

Indian journal of science and technology, 2015-08, Vol.8 (17), p.1-1

2015

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Self-gated resonant-clocked flip-flop optimised for power efficiency and signal integrity

IET circuits, devices & systems, 2016-03, Vol.10 (2), p.94-103

2016

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Boundary optimization of buffered clock trees for low power

Integration (Amsterdam), 2017-01, Vol.56, p.86-95

2017

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Robust Chip-Level Clock Tree Synthesis

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-06, Vol.30 (6), p.877-890

2011

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Hybrid Multisource Clock Tree Synthesis

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2021, p.1-6

Chong, Ang Boon

2021

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Comparative Analysis of the Characteristics of Clock Network Structures Buffer Tree, H-tree, Clock Mesh for Technological Nodes 28nm and 90nm

2024 IEEE 25th International Conference of Young Professionals in Electron Devices and Materials (EDM), 2024, p.270-279

Kuzmin, Pavel A.

2024

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Post Optimization of a Clock Tree for Dynamic Clock Tree Power Reduction in 45 nm and Below Technology Nodes

Journal of low-power electronics, 2014-03, Vol.10 (1), p.32-37

2014

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Clock Network Design Challenges

2023 IEEE XVI International Scientific and Technical Conference Actual Problems of Electronic Instrument Engineering (APEIE), 2023, p.110-117

Kuzmin, Pavel A.

2023

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Obstacle Avoiding Rectilinear Clock Tree Construction with Skew Minimization

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014, p.387-392

2014

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An Integrated Row-Based Cell Placement and Interconnect Synthesis Tool for Large SFQ Logic Circuits

IEEE transactions on applied superconductivity, 2017-06, Vol.27 (4), p.1-8

2017

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A novel scan segmentation design method for avoiding shift timing failure in scan testing

2011 IEEE International Test Conference, 2011, p.1-8

2011

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Harnessing Hybrid Clock Tree Topology to Boost PPA in Highly Utilized Designs

2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2023, p.299-303

2023

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A Clock Tree Prediction and Optimization Framework Using Generative Adversarial Learning

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-09, Vol.41 (9), p.3104-3117

2022

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CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing

IEEE transactions on very large scale integration (VLSI) systems, 2024-01, Vol.32 (1), p.137-149

2024

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单光子探测盖革雪崩焦平面用低抖动多相位时钟电路设计

电子与信息学报, 2021-06, Vol.43 (6), p.1565-1573

2021

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Mono3D: Open Source Cell Library for Monolithic 3-D Integrated Circuits

IEEE transactions on circuits and systems. I, Regular papers, 2018-03, Vol.65 (3), p.1075-1085

2018

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Pin-3D: Effective Physical Design Methodology for Multidie Co-Optimization in Monolithic 3-D ICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-04, Vol.43 (4), p.1009-1022

2024

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Design Automation Framework for Placement and Clock Tree Synthesis of Superconducting Rapid Single-Flux-Quantum Logic

IEEE transactions on applied superconductivity, 2023-12, Vol.33 (9), p.1-8

2023

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Asynchronous Event-Driven Clocking and Control in Pipelined ADCs

IEEE transactions on circuits and systems. I, Regular papers, 2021-07, Vol.68 (7), p.2813-2826

2021

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A Minimum-Skew Clock Tree Synthesis Algorithm for Single Flux Quantum Logic Circuits

IEEE transactions on applied superconductivity, 2019-12, Vol.29 (8), p.1-13

2019

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Design Automation of Series Resonance Clocking in 14-nm FinFETs

Circuits, systems, and signal processing, 2023-12, Vol.42 (12), p.7549-7579

2023

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180 Gbit/s 4:1 power multiplexer for NRZ-OOK signals with high output voltage swing in SiGe BiCMOS technology

Electronics letters, 2020-01, Vol.56 (2), p.69-71

2020

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Cross-Mesh Clock Network Synthesis

Electronics (Basel), 2023-08, Vol.12 (16), p.3410

2023

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Design Methodology for Voltage-Scaled Clock Distribution Networks

IEEE transactions on very large scale integration (VLSI) systems, 2016-10, Vol.24 (10), p.3080-3093

2016

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An algorithm for obstacle-avoiding clock routing tree construction with multiple TSVs on a 3D IC

Low Power Techniques for Digital System Design

Self-gated resonant-clocked flip-flop optimised for power efficiency and signal integrity

Boundary optimization of buffered clock trees for low power

Robust Chip-Level Clock Tree Synthesis

Hybrid Multisource Clock Tree Synthesis

Comparative Analysis of the Characteristics of Clock Network Structures Buffer Tree, H-tree, Clock Mesh for Technological Nodes 28nm and 90nm

Post Optimization of a Clock Tree for Dynamic Clock Tree Power Reduction in 45 nm and Below Technology Nodes

Clock Network Design Challenges

Obstacle Avoiding Rectilinear Clock Tree Construction with Skew Minimization

An Integrated Row-Based Cell Placement and Interconnect Synthesis Tool for Large SFQ Logic Circuits

A novel scan segmentation design method for avoiding shift timing failure in scan testing

Harnessing Hybrid Clock Tree Topology to Boost PPA in Highly Utilized Designs

A Clock Tree Prediction and Optimization Framework Using Generative Adversarial Learning

CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing

单光子探测盖革雪崩焦平面用低抖动多相位时钟电路设计

Mono3D: Open Source Cell Library for Monolithic 3-D Integrated Circuits

Pin-3D: Effective Physical Design Methodology for Multidie Co-Optimization in Monolithic 3-D ICs

Design Automation Framework for Placement and Clock Tree Synthesis of Superconducting Rapid Single-Flux-Quantum Logic

Asynchronous Event-Driven Clocking and Control in Pipelined ADCs

A Minimum-Skew Clock Tree Synthesis Algorithm for Single Flux Quantum Logic Circuits

Design Automation of Series Resonance Clocking in 14-nm FinFETs

180 Gbit/s 4:1 power multiplexer for NRZ-OOK signals with high output voltage swing in SiGe BiCMOS technology

Cross-Mesh Clock Network Synthesis

Design Methodology for Voltage-Scaled Clock Distribution Networks

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