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Feasibility Study of a Time-of-Flight Brain Positron Emission Tomography Employing Individual Channel Readout Electronics

Sensors (Basel, Switzerland), 2021-08, Vol.21 (16), p.5566

2021

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An efficient hardware implementation of the elliptic curve cryptographic processor over prime field, Fp

International journal of circuit theory and applications, 2020-08, Vol.48 (8), p.1256-1273

2020

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Front-End Gateway System With Serial Communication Protocol Conversion and Edge Computing Platforms

IEEE access, 2023-01, Vol.11, p.1-1

2023

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A Temperature-Compensated Single-Crystal Silicon-on-Insulator (SOI) MEMS Oscillator with a CMOS Amplifier Chip

Micromachines (Basel), 2018-10, Vol.9 (11), p.559

2018

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Low-Cost Low-Power ASIC Solution for Both DAB+ and DAB Audio Decoding

IEEE transactions on very large scale integration (VLSI) systems, 2014-04, Vol.22 (4), p.913-921

2014

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High-Throughput and High-Speed Polar-Decoder VLSI-Architecture for 5G New Radio

2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID), 2019, p.329-334

2019

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Development of CMOS-MEMS/NEMS Devices

2019

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A Review of New Time-to-Digital Conversion Techniques

IEEE transactions on instrumentation and measurement, 2019-10, Vol.68 (10), p.3406-3417

2019

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A Reconfigurable Neural Network ASIC for Detector Front-End Data Compression at the HL-LHC

IEEE transactions on nuclear science, 2021-08, Vol.68 (8), p.2179-2186

2021

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Novel logarithmic ECG feature extraction algorithm based on pan and tompkins

2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), 2016, p.1-4

2016

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A Transceiver ASIC for a Single-Cable 64-Element Intra-Vascular Ultrasound Probe

IEEE journal of solid-state circuits, 2021-10, Vol.56 (10), p.3157-3166

2021

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A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System on Chip

IEEE journal of solid-state circuits, 2021-08, Vol.56 (8), p.2476-2487

2021

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Custom Hardware Architectures for Deep Learning on Portable Devices: A Review

IEEE transaction on neural networks and learning systems, 2022-11, Vol.33 (11), p.6068-6088

2022

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ASIC Design and Synthesis: RTL Design Using Verilog

Taraate, Vaibbhav

1st Edition 2021, 2021

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Design of the Front-End Electronics for Silicon Beam Profilometer Prototype for Light Ions at the BM@N Experiment

IEEE transactions on nuclear science, 2022-03, Vol.69 (3), p.634-638

2022

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ANP-I: A 28-nm 1.5-pJ/SOP Asynchronous Spiking Neural Network Processor Enabling Sub-0.1-μ J/Sample On-Chip Learning for Edge-AI Applications

IEEE journal of solid-state circuits, 2024-08, Vol.59 (8), p.2717-2729

2024

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A Variable-Gain Low-Noise Transimpedance Amplifier for Miniature Ultrasound Probes

IEEE journal of solid-state circuits, 2020-12, Vol.55 (12), p.3157-3168

2020

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Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology

Proceedings of the IEEE, 2015-03, Vol.103 (3), p.318-331

Trimberger, Stephen M.

2015

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Integrated Circuit for Magnetic Encoder Sensing in TMR-Based Industrial Positioning System

IEEE transactions on industrial electronics (1982), 2024-08, Vol.71 (8), p.1-10

2024

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Design and Test of a Time-to-Digital Converter ASIC Based on a Differential Delay Line

IEEE transactions on nuclear science, 2024-08, Vol.71 (8), p.2020-2025

2024

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A 125 μ m-Pitch-Matched Transceiver ASIC With Micro-Beamforming ADC and Multi-Level Signaling for 3-D Transfontanelle Ultrasonography

IEEE journal of solid-state circuits, 2024-08, Vol.59 (8), p.2604-2617

2024

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High-Resolution Nondestructive Test Probes Based on Magnetoresistive Sensors

IEEE transactions on industrial electronics (1982), 2019-09, Vol.66 (9), p.7326-7337

2019

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An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In Situ Personalization on Smart Devices

IEEE journal of solid-state circuits, 2020-10, Vol.55 (10), p.2691-2702

2020

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The Heterogeneous Deep Neural Network Processor With a Non-von Neumann Architecture

Proceedings of the IEEE, 2020-08, Vol.108 (8), p.1245-1260

2020

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Cryogenic electronics for noble liquid neutrino detectors

Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment, 2023-01, Vol.1045, p.167571, Article 167571

2023

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Feasibility Study of a Time-of-Flight Brain Positron Emission Tomography Employing Individual Channel Readout Electronics

An efficient hardware implementation of the elliptic curve cryptographic processor over prime field, Fp

Front-End Gateway System With Serial Communication Protocol Conversion and Edge Computing Platforms

A Temperature-Compensated Single-Crystal Silicon-on-Insulator (SOI) MEMS Oscillator with a CMOS Amplifier Chip

Low-Cost Low-Power ASIC Solution for Both DAB+ and DAB Audio Decoding

High-Throughput and High-Speed Polar-Decoder VLSI-Architecture for 5G New Radio

Development of CMOS-MEMS/NEMS Devices

A Review of New Time-to-Digital Conversion Techniques

A Reconfigurable Neural Network ASIC for Detector Front-End Data Compression at the HL-LHC

Novel logarithmic ECG feature extraction algorithm based on pan and tompkins

A Transceiver ASIC for a Single-Cable 64-Element Intra-Vascular Ultrasound Probe

A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System on Chip

Custom Hardware Architectures for Deep Learning on Portable Devices: A Review

ASIC Design and Synthesis: RTL Design Using Verilog

Design of the Front-End Electronics for Silicon Beam Profilometer Prototype for Light Ions at the BM@N Experiment

ANP-I: A 28-nm 1.5-pJ/SOP Asynchronous Spiking Neural Network Processor Enabling Sub-0.1-μ J/Sample On-Chip Learning for Edge-AI Applications

A Variable-Gain Low-Noise Transimpedance Amplifier for Miniature Ultrasound Probes

Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology

Integrated Circuit for Magnetic Encoder Sensing in TMR-Based Industrial Positioning System

Design and Test of a Time-to-Digital Converter ASIC Based on a Differential Delay Line

A 125 μ m-Pitch-Matched Transceiver ASIC With Micro-Beamforming ADC and Multi-Level Signaling for 3-D Transfontanelle Ultrasonography

High-Resolution Nondestructive Test Probes Based on Magnetoresistive Sensors

An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In Situ Personalization on Smart Devices

The Heterogeneous Deep Neural Network Processor With a Non-von Neumann Architecture

Cryogenic electronics for noble liquid neutrino detectors

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