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A 1.2V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package employing F-chip for low power and high performance storage applications

2017 Symposium on VLSI Circuits, 2017, p.C194-C195

2017

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An 1.4Gbps/ch LVDS Receiver with Jitter-Boundary-Based Digital De-skew Algorithm

2006 IEEE Asian Solid-State Circuits Conference, 2006, p.383-386

2006

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A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend

IEEE transactions on circuits and systems. II, Express briefs, 2023-02, Vol.70 (2), p.411-415

2023

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13.4 A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.216-218

2019

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19.2 A 93.4mm2 64Gb MLC NAND-flash memory with 16nm CMOS technology

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, p.328-329

2014

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A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth

2012 IEEE International Solid-State Circuits Conference, 2012, p.46-48

2012

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A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2021, p.1-3

2021

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28.2 A High-Performance 1Tb 3b/Cell 3D-NAND Flash with a 194MB/s Write Throughput on over 300 Layers \mathsf

2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023, p.27-29

2023

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A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021, p.463-466

2021

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A 32-Gb/s Single-Ended PAM-4 Transceiver With Asymmetric Termination and Equalization Techniques for Next-Generation Memory Interfaces

IEEE transactions on circuits and systems. I, Regular papers, 2024-06, p.1-12

2024

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A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3

IEEE journal of solid-state circuits, 2024-07, p.1-10

2024

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A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.148-149

2022

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A 430-MS/s 7-b Asynchronous SAR ADC With a 40 fF Input Sampling Capacitor

2022 19th International SoC Design Conference (ISOCC), 2022, p.235-236

2022

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A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3

2023 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2023, p.1-3

2023

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A 5 Gb/s 0.25 mu m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

Digest of technical papers - IEEE International Solid-State Circuits Conference, 2002-01, p.206-207+474

2002

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A 5 Gb/s 0.25 /spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002, Vol.1, p.256-465 vol.1

2002

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A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW

2011 IEEE International Solid-State Circuits Conference, 2011, p.500-502

2011

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A 5Gb/s 0.25/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002, Vol.2, p.206-474

2002

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A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process

2022 IEEE Custom Integrated Circuits Conference (CICC), 2022, p.1-2

2022

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Balance Deficit and Brain Connectivity in Children with Attention-Deficit/Hyperactivity Disorder

Psychiatry investigation, 2017-07, Vol.14 (4), p.452-457

2017

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BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel

IEEE journal of solid-state circuits, 2009-11, Vol.44 (11), p.2987-2998

2009

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Channel BER Measurement for a 5.8Gb/s/pin unidirectional differential I/O for DRAM application

2008 IEEE Asian Solid-State Circuits Conference, 2008, p.29-32

2008

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Deep-learning Based Adaptive Power Control on Common Data Link System

Journal of the Institute of Electronics and Information Engineers, 2017-11, Vol.54 (11), p.33-44

2017

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Differential Via Optimization for PCIe Gen5 Channel based on Particle Swarm Optimization Algorithm

2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2022, p.1-3

2022

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A Digital Temperature Sensor Based on 10b SAR ADC for Non-linear Temperature Dependency Compensation in 3D NAND Flash Memory

2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2022, p.1-3

2022

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A 1.2V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package employing F-chip for low power and high performance storage applications

An 1.4Gbps/ch LVDS Receiver with Jitter-Boundary-Based Digital De-skew Algorithm

A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend

13.4 A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface

19.2 A 93.4mm2 64Gb MLC NAND-flash memory with 16nm CMOS technology

A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth

A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE

28.2 A High-Performance 1Tb 3b/Cell 3D-NAND Flash with a 194MB/s Write Throughput on over 300 Layers \mathsf

A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics

A 32-Gb/s Single-Ended PAM-4 Transceiver With Asymmetric Termination and Equalization Techniques for Next-Generation Memory Interfaces

A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3

A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application

A 430-MS/s 7-b Asynchronous SAR ADC With a 40 fF Input Sampling Capacitor

A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3

A 5 Gb/s 0.25 mu m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

A 5 Gb/s 0.25 /spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW

A 5Gb/s 0.25/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process

Balance Deficit and Brain Connectivity in Children with Attention-Deficit/Hyperactivity Disorder

BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel

Channel BER Measurement for a 5.8Gb/s/pin unidirectional differential I/O for DRAM application

Deep-learning Based Adaptive Power Control on Common Data Link System

Differential Via Optimization for PCIe Gen5 Channel based on Particle Swarm Optimization Algorithm

A Digital Temperature Sensor Based on 10b SAR ADC for Non-linear Temperature Dependency Compensation in 3D NAND Flash Memory

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