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OxRRAM-Based Analog in-Memory Computing for Deep Neural Network Inference: A Conductance Variability Study

IEEE transactions on electron devices, 2021-05, Vol.68 (5), p.2301-2305

2021

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IGZO-Based Compute Cell for Analog In-Memory Computing-DTCO Analysis to Enable Ultralow-Power AI at Edge

IEEE transactions on electron devices, 2020-11, Vol.67 (11), p.4616-4620

2020

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SOT-MRAM Based Analog in-Memory Computing for DNN Inference

2020 IEEE Symposium on VLSI Technology, 2020, p.1-2

2020

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3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot

Proceedings of the IEEE, 2009-01, Vol.97 (1), p.96-107

2009

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Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip

IEEE transactions on computers, 2008-09, Vol.57 (9), p.1182-1195

2008

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A Coarse-Grained Array Accelerator for Software-Defined Radio Baseband Processing

IEEE MICRO, 2008-07, Vol.28 (4), p.41-50

2008

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Run-Time Management of a MPSoC Containing FPGA Fabric Tiles

IEEE transactions on very large scale integration (VLSI) systems, 2008-01, Vol.16 (1), p.24-33

2008

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Economics of semiconductor scaling - a cost analysis for advanced technology node

2019 Symposium on VLSI Technology, 2019, p.T202-T203

2019

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Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study

Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004, Vol.2, p.1224-1229 Vol.2

2004

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Holisitic device exploration for 7nm node

2015 IEEE Custom Integrated Circuits Conference (CICC), 2015, p.1-5

2015

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Vertical device architecture for 5nm and beyond: Device & circuit implications

2015 Symposium on VLSI Technology (VLSI Technology), 2015, p.T26-T27

2015

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Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures

IEEE transactions on computers, 2009-03, Vol.58 (3), p.311-321

2009

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Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures

IEEE transactions on very large scale integration (VLSI) systems, 2009-01, Vol.17 (1), p.151-155

2009

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Characterization and simulation methodology for time-dependent variability in advanced technologies

2015 IEEE Custom Integrated Circuits Conference (CICC), 2015, p.1-8

2015

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Novel forksheet device architecture as ultimate logic scaling device towards 2nm

2019 IEEE International Electron Devices Meeting (IEDM), 2019, p.36.5.1-36.5.4

2019

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Enabling Sub-5nm CMOS Technology Scaling Thinner and Taller

2019 IEEE International Electron Devices Meeting (IEDM), 2019, p.29.4.1-29.4.4

2019

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Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling

2003 Design, Automation and Test in Europe Conference and Exhibition, 2003, p.296-301

2003

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Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology

2017 IEEE International Electron Devices Meeting (IEDM), 2017, p.20.4.1-20.4.4

2017

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ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix

Field Programmable Logic and Application, 2003, p.61-70

2003

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Operating system based software generation for systems-on-chip

Proceedings - ACM IEEE Design Automation Conference, 2000, p.396-401

2000

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Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles

Design, Automation and Test in Europe, 2005, p.234-239

2005

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Device-, Circuit- & Block-level evaluation of CFET in a 4 track library

2019 Symposium on VLSI Technology, 2019, p.T204-T205

2019

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Networks on Chip as Hardware Components of an OS for Reconfigurable Systems

Field Programmable Logic and Application, 2003, p.595-605

2003

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Operating-system controlled network on chip

Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004, 2004, p.256-259

2004

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Power-performance Trade-offs for Lateral NanoSheets on Ultra-Scaled Standard Cells

2018 IEEE Symposium on VLSI Technology, 2018, p.143-144

2018

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OxRRAM-Based Analog in-Memory Computing for Deep Neural Network Inference: A Conductance Variability Study

IGZO-Based Compute Cell for Analog In-Memory Computing-DTCO Analysis to Enable Ultralow-Power AI at Edge

SOT-MRAM Based Analog in-Memory Computing for DNN Inference

3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot

Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip

A Coarse-Grained Array Accelerator for Software-Defined Radio Baseband Processing

Run-Time Management of a MPSoC Containing FPGA Fabric Tiles

Economics of semiconductor scaling - a cost analysis for advanced technology node

Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study

Holisitic device exploration for 7nm node

Vertical device architecture for 5nm and beyond: Device & circuit implications

Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures

Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures

Characterization and simulation methodology for time-dependent variability in advanced technologies

Novel forksheet device architecture as ultimate logic scaling device towards 2nm

Enabling Sub-5nm CMOS Technology Scaling Thinner and Taller

Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling

Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology

ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix

Operating system based software generation for systems-on-chip

Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles

Device-, Circuit- & Block-level evaluation of CFET in a 4 track library

Networks on Chip as Hardware Components of an OS for Reconfigurable Systems

Operating-system controlled network on chip

Power-performance Trade-offs for Lateral NanoSheets on Ultra-Scaled Standard Cells

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