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An Intermodulation Radar for Non-Linear Target and Transceiver Detection

Sensors (Basel, Switzerland), 2024-02, Vol.24 (5), p.1433

2024

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New Models for the Calibration of Four-Channel Time-Interleaved ADCs Using Filter Banks

IEEE transactions on circuits and systems. II, Express briefs, 2018-02, Vol.65 (2), p.141-145

2018

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IEEE_Xplore

Subsampling Models of Bandwidth Mismatch for Time-Interleaved Converter Calibration

IEEE transactions on circuits and systems. II, Express briefs, 2015-10, Vol.62 (10), p.957-961

2015

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IEEE_Xplore

Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks

IEEE transactions on very large scale integration (VLSI) systems, 2018-07, Vol.26 (7), p.1368-1376

2018

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IEEE_Xplore

A novel parallel digitizer with a pulseless mixing-filtering-processing architecture and its implementation in a SiGe HBT technology at 40GS/s

IEEE access, 2023-01, Vol.11, p.1-1

2023

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A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

Journal of low power electronics and applications, 2022-03, Vol.12 (1), p.12

2022

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A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

Journal of low power electronics and applications, 2021-06, Vol.11 (2), p.19

2021

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A 0.3 V, Rail-to-Rail, Ultralow-Power, Non-Tailed, Body-Driven, Sub-Threshold Amplifier

Applied sciences, 2021-03, Vol.11 (6), p.2528

2021

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A 0.3V Rail-to-Rail Three-Stage OTA with High DC Gain and Improved Robustness to PVT Variations

IEEE access, 2023-01, Vol.11, p.1-1

2023

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An Improved Strong Arm Comparator with Integrated Static Preamplifier

IEEE access, 2023-01, Vol.11, p.1-1

2023

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Body Biasing Techniques for Dynamic Comparators: A Systematic Survey

Electronics (Basel), 2024-02, Vol.13 (4), p.711

2024

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Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters

IEEE transactions on circuits and systems. I, Regular papers, 2012-07, Vol.59 (7), p.1373-1383

2012

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IEEE_Xplore

A Differential-to-Single-Ended Converter Based on Enhanced Body-Driven Current Mirrors Targeting Ultra-Low-Voltage OTAs

Electronics (Basel), 2022-12, Vol.11 (23), p.3838

2022

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A 0.15-to-0.5 V Body-Driven Dynamic Comparator with Rail-to-Rail ICMR

Journal of low power electronics and applications, 2023-06, Vol.13 (2), p.35

2023

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A Detailed Model of the Switched-Resistor Technique

IEEE open journal of circuits and systems, 2021, Vol.2, p.497-507

2021

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A Novel OTA Architecture Exploiting Current Gain Stages to Boost Bandwidth and Slew-Rate

Electronics (Basel), 2021-07, Vol.10 (14), p.1638

2021

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Methods for Model Complexity Reduction for the Nonlinear Calibration of Amplifiers Using Volterra Kernels

Electronics (Basel), 2022-10, Vol.11 (19), p.3067

2022

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A New VCII Application: Sinusoidal Oscillators

Journal of low power electronics and applications, 2021-09, Vol.11 (3), p.30

2021

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Low power switched-resistor band-pass filter for neural recording channels in 130nm CMOS

Heliyon, 2020-08, Vol.6 (8), p.e04723-e04723, Article e04723

2020

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A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS

Electronics (Basel), 2020-11, Vol.9 (11), p.1968

2020

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A New Fully Closed-Loop, High-Precision, Class-AB CCII for Differential Capacitive Sensor Interfaces

Electronics (Basel), 2022-03, Vol.11 (6), p.903

2022

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10-GHz Fully Differential Sallen–Key Lowpass Biquad Filters in 55nm SiGe BiCMOS Technology

Electronics (Basel), 2020-04, Vol.9 (4), p.563

2020

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A Flip-Flop for the DPA Resistant Three-Phase Dual-Rail Pre-Charge Logic Family

IEEE transactions on very large scale integration (VLSI) systems, 2012-11, Vol.20 (11), p.2128-2132

2012

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IEEE_Xplore

A Novel 0.5 V MCML D-Flip-Flop Topology Exploiting Forward Body Bias Threshold Lowering

IEEE transactions on circuits and systems. II, Express briefs, 2020-03, Vol.67 (3), p.560-564

2020

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IEEE_Xplore

Faster, Stabler, and Simpler-A Recursive-Least-Squares Algorithm Exploiting the Frisch-Waugh-Lovell Theorem

IEEE transactions on circuits and systems. II, Express briefs, 2017-03, Vol.64 (3), p.344-348

2017

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IEEE_Xplore

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An Intermodulation Radar for Non-Linear Target and Transceiver Detection

New Models for the Calibration of Four-Channel Time-Interleaved ADCs Using Filter Banks

Subsampling Models of Bandwidth Mismatch for Time-Interleaved Converter Calibration

Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks

A novel parallel digitizer with a pulseless mixing-filtering-processing architecture and its implementation in a SiGe HBT technology at 40GS/s

A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

A 0.3 V, Rail-to-Rail, Ultralow-Power, Non-Tailed, Body-Driven, Sub-Threshold Amplifier

A 0.3V Rail-to-Rail Three-Stage OTA with High DC Gain and Improved Robustness to PVT Variations

An Improved Strong Arm Comparator with Integrated Static Preamplifier

Body Biasing Techniques for Dynamic Comparators: A Systematic Survey

Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters

A Differential-to-Single-Ended Converter Based on Enhanced Body-Driven Current Mirrors Targeting Ultra-Low-Voltage OTAs

A 0.15-to-0.5 V Body-Driven Dynamic Comparator with Rail-to-Rail ICMR

A Detailed Model of the Switched-Resistor Technique

A Novel OTA Architecture Exploiting Current Gain Stages to Boost Bandwidth and Slew-Rate

Methods for Model Complexity Reduction for the Nonlinear Calibration of Amplifiers Using Volterra Kernels

A New VCII Application: Sinusoidal Oscillators

Low power switched-resistor band-pass filter for neural recording channels in 130nm CMOS

A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS

A New Fully Closed-Loop, High-Precision, Class-AB CCII for Differential Capacitive Sensor Interfaces

10-GHz Fully Differential Sallen–Key Lowpass Biquad Filters in 55nm SiGe BiCMOS Technology

A Flip-Flop for the DPA Resistant Three-Phase Dual-Rail Pre-Charge Logic Family

A Novel 0.5 V MCML D-Flip-Flop Topology Exploiting Forward Body Bias Threshold Lowering

Faster, Stabler, and Simpler-A Recursive-Least-Squares Algorithm Exploiting the Frisch-Waugh-Lovell Theorem

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