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Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs

IEEE transactions on circuits and systems. I, Regular papers, 2014-10, Vol.61 (10), p.2851-2861

2014

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Fpga Eda: Design Principles and Implementation

1, 2024

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A Study on the Programming Structures for RRAM-Based FPGA Architectures

IEEE transactions on circuits and systems. I, Regular papers, 2016-04, Vol.63 (4), p.503-516

2016

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Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure

IEEE transactions on circuits and systems. I, Regular papers, 2017-05, Vol.64 (5), p.1173-1186

2017

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A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells

IEEE transactions on very large scale integration (VLSI) systems, 2015-10, Vol.23 (10), p.2187-2197

2015

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A High-Performance FPGA Architecture Using One-Level RRAM-Based Multiplexers

IEEE transactions on emerging topics in computing, 2017-04, Vol.5 (2), p.210-222

2017

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Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise

IEEE transactions on very large scale integration (VLSI) systems, 2013-12, Vol.21 (12), p.2226-2239

2013

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FPGA EDA: Design Principles and Implementation

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TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014, p.1660-1663

2014

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A ultra-low-power FPGA based on monolithically integrated RRAMs

2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, p.1203-1208

2015

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A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom FPGA Design

IEEE transactions on very large scale integration (VLSI) systems, 2023-08, Vol.31 (8), p.1128-1139

2023

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OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs

IEEE MICRO, 2020-07, Vol.40 (4), p.41-48

2020

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FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

IEEE transactions on very large scale integration (VLSI) systems, 2019-03, Vol.27 (3), p.637-650

2019

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Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction

IEEE transactions on very large scale integration (VLSI) systems, 2023-10, Vol.31 (10), p.1-13

2023

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Smart-Redundancy: An Alternative SEU/SET Mitigation Method for FPGAs

2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, p.1-5

2021

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Exploring eFPGA-based Redaction for IP Protection

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021, p.1-9

2021

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Post-P&R Performance and Power Analysis for RRAM-Based FPGAs

IEEE journal on emerging and selected topics in circuits and systems, 2018-09, Vol.8 (3), p.639-650

2018

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A high-performance low-power near-Vt RRAM-based FPGA

2014 International Conference on Field-Programmable Technology (FPT), 2014, p.207-214

2014

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A RRAM-based FPGA for Energy-efficient Edge Computing

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, p.144-a-144-f

2020

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Invited: Getting the Most out of your Circuits with Heterogeneous Logic Synthesis

2021 58th ACM/IEEE Design Automation Conference (DAC), 2021, p.1331-1334

2021

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A RRAM-based FPGA for energy-efficient edge computing

Proceedings of the 23rd Conference on Design, Automation and Test in Europe, 2020, p.144a-144

2020

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ALICE: an automatic design flow for eFPGA redaction

Proceedings of the 59th ACM/IEEE Design Automation Conference, 2022, p.781-786

2022

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Optimization opportunities in RRAM-based FPGA architectures

2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), 2017, p.1-4

2017

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A scalable mixed synthesis framework for heterogeneous networks

Proceedings of the 23rd Conference on Design, Automation and Test in Europe, 2020, p.670-673

2020

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A Scalable Mixed Synthesis Framework for Heterogeneous Networks

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, p.670-673

2020

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Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs

Fpga Eda: Design Principles and Implementation

A Study on the Programming Structures for RRAM-Based FPGA Architectures

Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure

A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells

A High-Performance FPGA Architecture Using One-Level RRAM-Based Multiplexers

Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise

FPGA EDA: Design Principles and Implementation

TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs

A ultra-low-power FPGA based on monolithically integrated RRAMs

A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom FPGA Design

OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction

Smart-Redundancy: An Alternative SEU/SET Mitigation Method for FPGAs

Exploring eFPGA-based Redaction for IP Protection

Post-P&R Performance and Power Analysis for RRAM-Based FPGAs

A high-performance low-power near-Vt RRAM-based FPGA

A RRAM-based FPGA for Energy-efficient Edge Computing

Invited: Getting the Most out of your Circuits with Heterogeneous Logic Synthesis

A RRAM-based FPGA for energy-efficient edge computing

ALICE: an automatic design flow for eFPGA redaction

Optimization opportunities in RRAM-based FPGA architectures

A scalable mixed synthesis framework for heterogeneous networks

A Scalable Mixed Synthesis Framework for Heterogeneous Networks

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