UB Paderborn / Katalog / Suche / in CDI

Sortiert nach

Einfacher Volltextzugriff von (fast) überall

Installieren Sie die LibKey Nomad-Browsererweiterung und erhalten Sie von vielen Webseiten einfachen Zugriff auf lizenzierte Volltexte oder Open Access Publikationen. Mehr erfahren...

Relationship between needle depth for lumbar transforaminal epidural injection and patients' height and weight using magnetic resonance imaging

The Korean Journal of Pain, 2022, 35(3), , pp.345-352

2022

Volltextzugriff (PDF)

Relationship between needle depth for lumbar transforaminal epidural injection and patients’ height and weight using magnetic resonance imaging

The Korean journal of pain, 2022-07, Vol.35 (3), p.345-352

2022

Volltextzugriff (PDF)

A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution

IEEE journal of solid-state circuits, 2017-01, Vol.52 (1), p.250-260

2017

Volltextzugriff (PDF)

An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process

IEEE access, 2021, Vol.9, p.33487-33497

2021

Volltextzugriff (PDF)

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

IEEE journal of solid-state circuits, 2013-01, Vol.48 (1), p.168-177

2013

Volltextzugriff (PDF)

Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product

2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), 2021, p.43-56

2021

Volltextzugriff (PDF)

An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s

IEEE journal of solid-state circuits, 2023-11, Vol.58 (11), p.1-11

2023

Volltextzugriff (PDF)

Near-Memory Processing in Action: Accelerating Personalized Recommendation With AxDIMM

IEEE MICRO, 2022-01, Vol.42 (1), p.116-127

2022

Volltextzugriff (PDF)

A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC

IEEE journal of solid-state circuits, 2022-06, Vol.57 (6), p.1913-1923

2022

Volltextzugriff (PDF)

Hardware architecture and software stack for PIM based on commercial DRAM technology

Proceedings of the 48th Annual International Symposium on Computer Architecture, 2021, p.43-56

2021

Volltextzugriff (PDF)

25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.350-352

2021

Volltextzugriff (PDF)

Dyamond: A 1T1C DRAM In-memory Computing Accelerator with Compact MAC-SIMD and Adaptive Column Addition Dataflow

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

Volltextzugriff (PDF)

Aquabolt-XL HBM2-PIM, LPDDR5-PIM With In-Memory Processing, and AXDIMM With Acceleration Buffer

IEEE MICRO, 2022-05, Vol.42 (3), p.20-30

2022

Volltextzugriff (PDF)

HBM3 RAS: Enhancing Resilience at Scale

IEEE computer architecture letters, 2021-07, Vol.20 (2), p.158-161

2021

Volltextzugriff (PDF)

A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme

IEEE journal of solid-state circuits, 2021-01, Vol.56 (1), p.199-211

2021

Volltextzugriff (PDF)

A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features

IEEE journal of solid-state circuits, 2023-04, Vol.58 (4), p.1051-1061

2023

Volltextzugriff (PDF)

The Breakthrough Memory Solutions for Improved Performance on LLM Inference

IEEE MICRO, 2024-05, Vol.44 (3), p.40-48

2024

Volltextzugriff (PDF)

Highly Accurate, Fully Digital Temperature Sensor With Curvature Correction

IEEE sensors journal, 2021-10, Vol.21 (19), p.21248-21258

2021

Volltextzugriff (PDF)

A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme

2012 IEEE International Solid-State Circuits Conference, 2012, p.38-40

2012

Volltextzugriff (PDF)

A Low-power Star-topology Body Area Network Controller for Periodic Data Monitoring Around and Inside the Human Body

2006 10th IEEE International Symposium on Wearable Computers, 2006, p.139-140

2006

Volltextzugriff (PDF)

A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, p.1-2

2023

Volltextzugriff (PDF)

A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.152-153

2022

Volltextzugriff (PDF)

22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.330-332

2020

Volltextzugriff (PDF)

An Embedded 8-bit RISC Controller for Yield Enhancement of the 90-nm PRAM

2007 IEEE Custom Integrated Circuits Conference, 2007, p.787-790

2007

Volltextzugriff (PDF)

A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.130-131

2022

Volltextzugriff (PDF)

1 – 25 von 56

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(25)
Mit Volltextzugriff
(50)

Publikationsform

Artikel
(28)
Tagungsberichte
(28)

Sprache

Erscheinungsjahr

n.n

Thema

Science & Technology
(33)
Technology
(25)
Random Access Memory
(20)
Engineering
(19)
Engineering, Electrical & Electronic
(19)
Bandwidth
(16)
Integrated Circuits
(11)
Computer Architecture
(10)
Computer Science
(9)
Energy Efficiency
(9)
Life Sciences & Biomedicine
(9)
Computer Science, Hardware & Architecture
(8)
Energy Consumption
(8)
Humans
(8)
Microprocessors
(8)
Through-Silicon Vias
(8)
Clinical Neurology
(7)
Neurosciences & Neurology
(7)
Timing
(7)
Voltage
(7)

15 weitere anzeigen...

Weniger anzeigen...

Neu hinzugefügt

... seit 30 Tagen
(1)

Menü

Weitere Dienste

Einstellungen

Relationship between needle depth for lumbar transforaminal epidural injection and patients' height and weight using magnetic resonance imaging

Relationship between needle depth for lumbar transforaminal epidural injection and patients’ height and weight using magnetic resonance imaging

A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution

An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product

An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s

Near-Memory Processing in Action: Accelerating Personalized Recommendation With AxDIMM

A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC

Hardware architecture and software stack for PIM based on commercial DRAM technology

25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications

Dyamond: A 1T1C DRAM In-memory Computing Accelerator with Compact MAC-SIMD and Adaptive Column Addition Dataflow

Aquabolt-XL HBM2-PIM, LPDDR5-PIM With In-Memory Processing, and AXDIMM With Acceleration Buffer

HBM3 RAS: Enhancing Resilience at Scale

A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme

A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features

The Breakthrough Memory Solutions for Improved Performance on LLM Inference

Highly Accurate, Fully Digital Temperature Sensor With Curvature Correction

A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme

A Low-power Star-topology Body Area Network Controller for Periodic Data Monitoring Around and Inside the Human Body

A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC

A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM

22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme

An Embedded 8-bit RISC Controller for Yield Enhancement of the 90-nm PRAM

A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features

Suchergebnisse filtern