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Field-Effect Transistors Built from All Two-Dimensional Material Components

ACS nano, 2014-06, Vol.8 (6), p.6259-6264

2014

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High-Gain Inverters Based on WSe2 Complementary Field-Effect Transistors

ACS nano, 2014-05, Vol.8 (5), p.4948-4953

2014

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Monolithic 3D CMOS Using Layered Semiconductors

Advanced materials (Weinheim), 2016-04, Vol.28 (13), p.2547-2554

2016

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Gate Fringe-Induced Barrier Lowering in Underlap FinFET Structures and Its Optimization

IEEE electron device letters, 2008-01, Vol.29 (1), p.128-130

2008

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MoS₂ transistors with 1-nanometer gate lengths

Science (American Association for the Advancement of Science), 2016-10, Vol.354 (6308), p.99-102

2016

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Improved Subthreshold Swing and Short Channel Effect in FDSOI n-Channel Negative Capacitance Field Effect Transistors

IEEE electron device letters, 2018-02, Vol.39 (2), p.300-303

2018

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Denser and More Stable SRAM Using FinFETs With Multiple Fin Heights

IEEE transactions on electron devices, 2012-08, Vol.59 (8), p.2037-2041

2012

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High-gain monolithic 3D CMOS inverter using layered semiconductors

Applied physics letters, 2017-11, Vol.111 (22)

2017

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Insights Into the Design and Optimization of Tunnel-FET Devices and Circuits

IEEE transactions on electron devices, 2011-04, Vol.58 (4), p.1045-1053

2011

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Variation Caused by Spatial Distribution of Dielectric and Ferroelectric Grains in a Negative Capacitance Field-Effect Transistor

IEEE transactions on electron devices, 2018-10, Vol.65 (10), p.4652-4658

2018

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Modeling of Back-Gate Effects on Gate-Induced Drain Leakage and Gate Currents in UTB SOI MOSFETs

IEEE transactions on electron devices, 2017-10, Vol.64 (10), p.3986-3990

2017

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Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect

2018 IEEE Symposium on VLSI Technology, 2018, p.53-54

2018

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A Novel and Robust Approach for Common Mode Feedback Using IDDG FinFET

IEEE transactions on electron devices, 2008-11, Vol.55 (11), p.3274-3282

2008

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Impact of Fringe Capacitance on the Performance of Nanoscale FinFETs

IEEE electron device letters, 2010-01, Vol.31 (1), p.83-85

2010

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FinFET With High- \kappa Spacers for Improved Drive Current

IEEE electron device letters, 2016-07, Vol.37 (7), p.835-838

2016

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Bulk FinFET With Low- \kappa Spacers for Continued Scaling

IEEE transactions on electron devices, 2017-04, Vol.64 (4), p.1861-1864

2017

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Engineering Negative Differential Resistance in NCFETs for Analog Applications

IEEE transactions on electron devices, 2018-05, Vol.65 (5), p.2033-2039

2018

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Nanowire FET With Corner Spacer for High-Performance, Energy-Efficient Applications

IEEE transactions on electron devices, 2017-12, Vol.64 (12), p.5181-5187

2017

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Drain current model for nanoscale double-gate MOSFETs

Solid-state electronics, 2009-09, Vol.53 (9), p.1001-1008

2009

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UTBSOI MOSFET with corner spacers for energy-efficient applications

2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2018, p.1-2

2018

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FinFET With High-[Formula Omitted] Spacers for Improved Drive Current

IEEE electron device letters, 2016-07, Vol.37 (7), p.835

2016

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FinFET With Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits

IEEE electron device letters, 2017-01, Vol.38 (1), p.16-19

2017

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Designing 0.5 V 5-nm HP and 0.23 V 5-nm LP NC-FinFETs With Improved } Sensitivity in Presence of Parasitic Capacitance

IEEE transactions on electron devices, 2018-03, Vol.65 (3), p.1211-1216

2018

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New Mobility Model for Accurate Modeling of Transconductance in FDSOI MOSFETs

IEEE transactions on electron devices, 2018-02, Vol.65 (2), p.463-469

2018

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MoS 2 transistors with 1-nanometer gate lengths

Science (American Association for the Advancement of Science), 2016-10, Vol.354 (6308), p.99-102

2016

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Field-Effect Transistors Built from All Two-Dimensional Material Components

High-Gain Inverters Based on WSe2 Complementary Field-Effect Transistors

Monolithic 3D CMOS Using Layered Semiconductors

Gate Fringe-Induced Barrier Lowering in Underlap FinFET Structures and Its Optimization

MoS₂ transistors with 1-nanometer gate lengths

Improved Subthreshold Swing and Short Channel Effect in FDSOI n-Channel Negative Capacitance Field Effect Transistors

Denser and More Stable SRAM Using FinFETs With Multiple Fin Heights

High-gain monolithic 3D CMOS inverter using layered semiconductors

Insights Into the Design and Optimization of Tunnel-FET Devices and Circuits

Variation Caused by Spatial Distribution of Dielectric and Ferroelectric Grains in a Negative Capacitance Field-Effect Transistor

Modeling of Back-Gate Effects on Gate-Induced Drain Leakage and Gate Currents in UTB SOI MOSFETs

Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect

A Novel and Robust Approach for Common Mode Feedback Using IDDG FinFET

Impact of Fringe Capacitance on the Performance of Nanoscale FinFETs

FinFET With High- \kappa Spacers for Improved Drive Current

Bulk FinFET With Low- \kappa Spacers for Continued Scaling

Engineering Negative Differential Resistance in NCFETs for Analog Applications

Nanowire FET With Corner Spacer for High-Performance, Energy-Efficient Applications

Drain current model for nanoscale double-gate MOSFETs

UTBSOI MOSFET with corner spacers for energy-efficient applications

FinFET With High-[Formula Omitted] Spacers for Improved Drive Current

FinFET With Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits

Designing 0.5 V 5-nm HP and 0.23 V 5-nm LP NC-FinFETs With Improved } Sensitivity in Presence of Parasitic Capacitance

New Mobility Model for Accurate Modeling of Transconductance in FDSOI MOSFETs

MoS 2 transistors with 1-nanometer gate lengths

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