UB Paderborn / Katalog / Suche / in CDI

Sortiert nach

Einfacher Volltextzugriff von (fast) überall

Installieren Sie die LibKey Nomad-Browsererweiterung und erhalten Sie von vielen Webseiten einfachen Zugriff auf lizenzierte Volltexte oder Open Access Publikationen. Mehr erfahren...

Low Cost Memristor Associative Memory Design for Full and Partial Matching Applications

IEEE transactions on nanotechnology, 2016-05, Vol.15 (3), p.527-538

2016

Volltextzugriff (PDF)

Energy-Aware Memory Management for Embedded Multimedia Systems: A Computer-Aided Design Approach

1, 2011

Volltextzugriff (PDF)

Complementary Resistive Switch-Based Arithmetic Logic Implementations Using Material Implication

IEEE transactions on nanotechnology, 2016-01, Vol.15 (1), p.94-108

2016

Volltextzugriff (PDF)

Matrix Codes for Reliable and Cost Efficient Memory Chips

IEEE transactions on very large scale integration (VLSI) systems, 2011-03, Vol.19 (3), p.420-428

2011

Volltextzugriff (PDF)

Instantaneous Mean-Time-To-Failure (MTTF) estimation for checkpoint interval computation at run time

Microelectronics and reliability, 2019-07, Vol.98, p.69-77

2019

Volltextzugriff (PDF)

A Low-Cost Unified Design Methodology for Secure Test and Intellectual Property Core Protection

IEEE transactions on reliability, 2015-12, Vol.64 (4), p.1243-1253

2015

Volltextzugriff (PDF)

A Novel Memristor-Based Hardware Security Primitive

ACM transactions on embedded computing systems, 2015-05, Vol.14 (3), p.1-20

2015

Volltextzugriff (PDF)

Matrix-Based Codes for Adjacent Error Correction

IEEE transactions on nuclear science, 2010-08, Vol.57 (4), p.2106-2111

2010

Volltextzugriff (PDF)

On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography

Theory of Quantum Computation, Communication, and Cryptography, p.96-104

Volltextzugriff (PDF)

NiVER: Non-increasing Variable Elimination Resolution for Preprocessing SAT Instances

Lecture notes in computer science, 2005, p.276-291

2005

Volltextzugriff (PDF)

Memristor Based Arbiter PUF: Cryptanalysis Threat and Its Mitigation

2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 2016, p.535-540

2016

Volltextzugriff (PDF)

Verilog-A Based Effective Complementary Resistive Switch Model for Simulations and Analysis

IEEE embedded systems letters, 2014-03, Vol.6 (1), p.12-15

2014

Volltextzugriff (PDF)

Test Generation in Systolic Architecture for Multiplication Over GF(2 ^)

IEEE transactions on very large scale integration (VLSI) systems, 2010-09, Vol.18 (9), p.1366-1371

2010

Volltextzugriff (PDF)

Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph

IEEE transactions on very large scale integration (VLSI) systems, 2011-08, Vol.19 (8), p.1469-1480

2011

Volltextzugriff (PDF)

Formal Model for the Reduction of the Dynamic Energy Consumption in Multi-Layer Memory Subsystems

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2008, Vol.E91-A (12), p.3559-3567

2008

Volltextzugriff (PDF)

Fault-tolerant de-Bruijn graph based multipurpose architecture and routing protocol for wireless sensor networks

International journal of sensor networks, 2011, Vol.10 (3), p.160

2011

Volltextzugriff (PDF)

Reliability Analysis of H-Tree Random Access Memories Implemented With Built in Current Sensors and Parity Codes for Multiple Bit Upset Correction

IEEE transactions on reliability, 2011-09, Vol.60 (3), p.528-537

2011

Volltextzugriff (PDF)

Statistical DOE–ILP based power–performance–process (P3) optimization of nano-CMOS SRAM

Integration (Amsterdam), 2012, Vol.45 (1), p.33-45

2012

Volltextzugriff (PDF)

Exploring error-tolerant low-power multiple-output read scheme for memristor-based memory arrays

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015, p.17-20

2015

Volltextzugriff (PDF)

Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity

Computers & electrical engineering, 2013-05, Vol.39 (4), p.1077-1087

2013

Volltextzugriff (PDF)

Energy-Aware Memory Management for Embedded Multimedia Systems

2011

Volltextzugriff (PDF)

Fault Tolerant Single Error Correction Encoders

Journal of electronic testing, 2011-04, Vol.27 (2), p.215-218

2011

Volltextzugriff (PDF)

Energy Efficient Lifetime Reliability-Aware Checkpointing for Real-Time System

Journal of low-power electronics, 2014-09, Vol.10 (3), p.401-416

2014

Volltextzugriff (PDF)

Design and Analysis of Binary Tree Static Random Access Memory for Low Power Embedded Systems

Journal of low-power electronics, 2014-09, Vol.10 (3), p.467-478

2014

Volltextzugriff (PDF)

A Routing-Aware ILS Design Technique

IEEE transactions on very large scale integration (VLSI) systems, 2011-12, Vol.19 (12), p.2335-2338

2011

Volltextzugriff (PDF)

1 – 25 von 285

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(157)
Mit Volltextzugriff
(270)

Publikationsform

1 weiteren anzeigen...

Weniger anzeigen...

Sprache

Englisch
(285)

Erscheinungsjahr

n.n

Thema

Science & Technology
(200)
Technology
(198)
Computer Science
(180)
Engineering
(133)
Engineering, Electrical & Electronic
(133)
Computer Science, Hardware & Architecture
(89)
Computer Science, Theory & Methods
(71)
Computer Science, Information Systems
(59)
Computer Science, Artificial Intelligence
(55)
Fault Tolerance
(47)
Circuit Faults
(40)
Applied Sciences
(39)
Exact Sciences And Technology
(39)
Hardware
(39)
Fault Detection
(28)
Dh-Hemts
(25)
Circuit Testing
(24)
Very Large Scale Integration
(22)
Electronics
(21)
Error Correction
(21)

15 weitere anzeigen...

Weniger anzeigen...

Menü

Weitere Dienste

Einstellungen

Low Cost Memristor Associative Memory Design for Full and Partial Matching Applications

Energy-Aware Memory Management for Embedded Multimedia Systems: A Computer-Aided Design Approach

Complementary Resistive Switch-Based Arithmetic Logic Implementations Using Material Implication

Matrix Codes for Reliable and Cost Efficient Memory Chips

Instantaneous Mean-Time-To-Failure (MTTF) estimation for checkpoint interval computation at run time

A Low-Cost Unified Design Methodology for Secure Test and Intellectual Property Core Protection

A Novel Memristor-Based Hardware Security Primitive

Matrix-Based Codes for Adjacent Error Correction

On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography

NiVER: Non-increasing Variable Elimination Resolution for Preprocessing SAT Instances

Memristor Based Arbiter PUF: Cryptanalysis Threat and Its Mitigation

Verilog-A Based Effective Complementary Resistive Switch Model for Simulations and Analysis

Test Generation in Systolic Architecture for Multiplication Over GF(2 ^)

Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph

Formal Model for the Reduction of the Dynamic Energy Consumption in Multi-Layer Memory Subsystems

Fault-tolerant de-Bruijn graph based multipurpose architecture and routing protocol for wireless sensor networks

Reliability Analysis of H-Tree Random Access Memories Implemented With Built in Current Sensors and Parity Codes for Multiple Bit Upset Correction

Statistical DOE–ILP based power–performance–process (P3) optimization of nano-CMOS SRAM

Exploring error-tolerant low-power multiple-output read scheme for memristor-based memory arrays

Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity

Energy-Aware Memory Management for Embedded Multimedia Systems

Fault Tolerant Single Error Correction Encoders

Energy Efficient Lifetime Reliability-Aware Checkpointing for Real-Time System

Design and Analysis of Binary Tree Static Random Access Memory for Low Power Embedded Systems

A Routing-Aware ILS Design Technique

Suchergebnisse filtern