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A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS

IEEE journal of solid-state circuits, 2016-10, Vol.51 (10), p.2357-2367

2016

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IEEE_Xplore

A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards

IEEE transactions on industrial electronics (1982), 2018-07, Vol.65 (7), p.5979-5989

2018

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IEEE_Xplore

A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver With Dead-Zone Free SS-MMSE PD for CIS Link

IEEE access, 2023, Vol.11, p.46513-46521

2023

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A 0.36 pJ/bit, 0.025 mm ^}, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology

IEEE transactions on circuits and systems. I, Regular papers, 2016-09, Vol.63 (9), p.1393-1403

2016

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IEEE_Xplore

A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS

IEEE access, 2021, Vol.9, p.156789-156798

2021

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A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel

IEEE transactions on circuits and systems. II, Express briefs, 2017-12, Vol.64 (12), p.1432-1436

2017

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IEEE_Xplore

A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control

2017 IEEE Custom Integrated Circuits Conference (CICC), 2017, p.1-4

2017

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IEEE_Xplore

A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference

IEEE journal of solid-state circuits, 2020-08, Vol.55 (8), p.2186-2195

2020

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IEEE_Xplore

Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector

IEEE journal of solid-state circuits, 2022-10, Vol.57 (10), p.3014-3024

2022

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IEEE_Xplore

A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS

IEEE journal of solid-state circuits, 2018-10, Vol.53 (10), p.2982-2993

2018

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IEEE_Xplore

A Low-Jitter Phase Detection Technique With Asymmetric Weights in Multi-Level Baud-Rate CDR

IEEE transactions on circuits and systems. I, Regular papers, 2024-05, p.1-12

2024

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IEEE_Xplore

An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS

IEEE journal of solid-state circuits, 2022-01, Vol.57 (1), p.21-31

2022

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IEEE_Xplore

Analysis of Stochastic Phase-Frequency Detector in 2x Oversampling Clock and Data Recovery

IEEE transactions on circuits and systems. II, Express briefs, 2024-04, Vol.71 (4), p.1-1

2024

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IEEE_Xplore

A 1.1-pJ/b 8-to-16-Gb/s Receiver with Stochastic CTLE Adaptation

IEEE transactions on circuits and systems. II, Express briefs, 2023-02, Vol.70 (2), p.1-1

2023

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IEEE_Xplore

A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS

IEEE journal of solid-state circuits, 2023-05, Vol.58 (5), p.1414-1424

2023

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IEEE_Xplore

A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS

IEEE journal of solid-state circuits, 2021-05, Vol.56 (5), p.1597-1607

2021

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IEEE_Xplore

A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, p.2389-2392

2015

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IEEE_Xplore

Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector

IEEE journal of solid-state circuits, 2022-02, Vol.57 (2), p.573-585

2022

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IEEE_Xplore

Analysis of frequency detection capability of Alexander phase detector

Electronics letters, 2020-02, Vol.56 (4), p.180-182

2020

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A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC), 2014, p.447-450

2014

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IEEE_Xplore

A 10-Gb/s, 0.03-mm 2 , 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology

IEEE journal of solid-state circuits, 2019-10, Vol.54 (10), p.2812-2822

2019

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A 2.44-pJ/b 1.62-10-Gb/s Receiver for Next Generation Video Interface Equalizing 23-dB Loss With Adaptive 2-Tap Data DFE and 1-Tap Edge DFE

IEEE transactions on circuits and systems. II, Express briefs, 2018-10, Vol.65 (10), p.1295-1299

2018

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IEEE_Xplore

8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.128-130

2021

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IEEE_Xplore

A Modulo-FIR Equalizer for Wireline Communications

IEEE transactions on circuits and systems. I, Regular papers, 2019-11, Vol.66 (11), p.4278-4286

2019

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IEEE_Xplore

An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2021-02, Vol.68 (2), p.622-626

2021

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IEEE_Xplore

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A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS

A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards

A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver With Dead-Zone Free SS-MMSE PD for CIS Link

A 0.36 pJ/bit, 0.025 mm ^}, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology

A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS

A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel

A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control

A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference

Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector

A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS

A Low-Jitter Phase Detection Technique With Asymmetric Weights in Multi-Level Baud-Rate CDR

An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS

Analysis of Stochastic Phase-Frequency Detector in 2x Oversampling Clock and Data Recovery

A 1.1-pJ/b 8-to-16-Gb/s Receiver with Stochastic CTLE Adaptation

A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS

A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS

A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS

Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector

Analysis of frequency detection capability of Alexander phase detector

A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line

A 10-Gb/s, 0.03-mm 2 , 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology

A 2.44-pJ/b 1.62-10-Gb/s Receiver for Next Generation Video Interface Equalizing 23-dB Loss With Adaptive 2-Tap Data DFE and 1-Tap Edge DFE

8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS

A Modulo-FIR Equalizer for Wireline Communications

An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS

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