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Parameter variations and impact on circuits and microarchitecture

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451), 2003, p.338-342

2003

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Functional Yield Estimation of Carbon Nanotube-Based Logic Gates in the Presence of Defects

IEEE transactions on nanotechnology, 2010-11, Vol.9 (6), p.687-700

2010

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MTCMOS hierarchical sizing based on mutual exclusive discharge patterns

Annual ACM IEEE Design Automation Conference: Proceedings of the 35th annual conference on Design automation; 15-19 June 1998, 1998, p.495-500

1998

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Challenges and design choices in nanoscale CMOS

ACM journal on emerging technologies in computing systems, 2005-03, Vol.1 (1), p.7-49

Narendra, Siva G.

2005

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Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor

IEEE transactions on very large scale integration (VLSI) systems, 2003-06, Vol.11 (3), p.514-522

2003

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The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance

IEEE transactions on electron devices, 2002-05, Vol.49 (5), p.826-831

2002

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The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance

IEEE transactions on electron devices, 2004-09, Vol.51 (9), p.1416-1423

2004

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Introduction to the Special Issue on the 2007 IEEE International Solid-State Circuits Conference

IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.3-5

2008

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Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage

IEEE journal of solid-state circuits, 2002-11, Vol.37 (11), p.1396-1402

2002

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An Online Integrated Development Environment (IDE) by using Lightweight Framework Render Studio

International Journal of Scientific Research in Computer Science, Engineering and Information Technology, 2022-06, p.299-303

2022

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A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

IEEE journal of solid-state circuits, 2005-04, Vol.40 (4), p.838-845

2005

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Dynamic sleep transistor and body bias for active leakage power control of microprocessors

IEEE journal of solid-state circuits, 2003-11, Vol.38 (11), p.1838-1845

2003

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Through the Looking Glass?The 2015 Edition: Trends in Solid-State Circuits from ISSCC

IEEE solid state circuits magazine, 2015-01, Vol.7 (1), p.14-24

2015

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Cascode Monolithic DC-DC Converter for Reliable Operation at High Input Voltages

Analog integrated circuits and signal processing, 2005-03, Vol.42 (3), p.231-238

2005

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Full-Chip Subthreshold Leakage Power Prediction and Reduction Techniques for Sub-0.18- $mu$ m CMOS

IEEE journal of solid-state circuits, 2004-03, Vol.39 (3), p.501-510

2004

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Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors

IEEE journal of solid-state circuits, 2003-05, Vol.38 (5), p.826-829

2003

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Forward body bias for microprocessors in 130-nm technology generation and beyond

IEEE journal of solid-state circuits, 2003-05, Vol.38 (5), p.696-701

2003

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Low-voltage-swing monolithic dc-dc conversion

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2004-05, Vol.51 (5), p.241-248

2004

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EP1: Next-generation networked systems-challenges for silicon

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, p.524-524

2014

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Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007, p.292-604

2007

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Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/T/ CMOS process

IEEE journal of solid-state circuits, 2004-09, Vol.39 (9), p.1536-1543

2004

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Scaling of stack effect and its application for leakage reduction

International Symposium on Low Power Electronics and Design: Proceedings of the 2001 international symposium on Low power electronics and design, 2001, p.195-200

2001

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Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

IEEE transactions on electron devices, 2003-04, Vol.50 (4), p.959-966

2003

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F4: Power Systems from the Gigawatt to the Microwatt - Generation, Distribution, Storage and Efficient Use of Energy

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.656-657

2008

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TD: Trends in Wireless Systems

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007, p.566-567

2007

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Parameter variations and impact on circuits and microarchitecture

Functional Yield Estimation of Carbon Nanotube-Based Logic Gates in the Presence of Defects

MTCMOS hierarchical sizing based on mutual exclusive discharge patterns

Challenges and design choices in nanoscale CMOS

Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor

The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance

The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance

Introduction to the Special Issue on the 2007 IEEE International Solid-State Circuits Conference

Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage

An Online Integrated Development Environment (IDE) by using Lightweight Framework Render Studio

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

Dynamic sleep transistor and body bias for active leakage power control of microprocessors

Through the Looking Glass?The 2015 Edition: Trends in Solid-State Circuits from ISSCC

Cascode Monolithic DC-DC Converter for Reliable Operation at High Input Voltages

Full-Chip Subthreshold Leakage Power Prediction and Reduction Techniques for Sub-0.18- $mu$ m CMOS

Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors

Forward body bias for microprocessors in 130-nm technology generation and beyond

Low-voltage-swing monolithic dc-dc conversion

EP1: Next-generation networked systems-challenges for silicon

Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/T/ CMOS process

Scaling of stack effect and its application for leakage reduction

Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

F4: Power Systems from the Gigawatt to the Microwatt - Generation, Distribution, Storage and Efficient Use of Energy

TD: Trends in Wireless Systems

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