UB Paderborn / Katalog / Suche / in CDI

1 – 25 von 64

Sortiert nach

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

ACM transactions on design automation of electronic systems, 2016-09, Vol.21 (4), p.1-25

2016

Link zum Volltext

Verfügbarkeit prüfen

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

IEEE transactions on circuits and systems. I, Regular papers, 2016-06, Vol.63 (6), p.806-817

2016

Link zum Volltext
IEEE_Xplore

An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and } Optimization

IEEE journal of solid-state circuits, 2019-01, Vol.54 (1), p.144-157

2019

Link zum Volltext
IEEE_Xplore

Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-On-Chip

1, 2017

Link zum Volltext

Verfügbarkeit prüfen

Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling

Journal of low power electronics and applications, 2013-04, Vol.3 (2), p.54-72

2013

Link zum Volltext

Verfügbarkeit prüfen

Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS

IEEE solid-state circuits letters, 2019-09, Vol.2 (9), p.147-150

2019

Link zum Volltext
IEEE_Xplore

A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC), 2014, p.243-246

2014

Link zum Volltext
IEEE_Xplore

A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS

2012 Proceedings of the ESSCIRC (ESSCIRC), 2012, p.321-324

2012

Link zum Volltext
IEEE_Xplore

Impact of body biasing on the retention time of gain-cell memories

Journal of engineering (Stevenage, England), 2013-08, Vol.2013 (8), p.19-22

2013

Link zum Volltext

Verfügbarkeit prüfen

Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation

IEEE transactions on circuits and systems. II, Express briefs, 2017-12, Vol.64 (12), p.1362-1366

2017

Link zum Volltext
IEEE_Xplore

A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications

IEEE transactions on very large scale integration (VLSI) systems, 2016-08, Vol.24 (8), p.2622-2633

2016

Link zum Volltext
IEEE_Xplore

Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs

IEEE transactions on circuits and systems. I, Regular papers, 2016-02, Vol.63 (2), p.222-232

2016

Link zum Volltext
IEEE_Xplore

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

IEEE transactions on circuits and systems. I, Regular papers, 2014-11, Vol.61 (11), p.3155-3164

2014

Link zum Volltext
IEEE_Xplore

Benchmarking of Standard-Cell Based Memories in the Sub- V Domain in 65-nm CMOS Technology

IEEE journal on emerging and selected topics in circuits and systems, 2011-06, Vol.1 (2), p.173-182

2011

Link zum Volltext
IEEE_Xplore

An All-Digital, V} -Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop

IEEE journal of solid-state circuits, 2020-07, Vol.55 (7), p.1898-1908

2020

Link zum Volltext
IEEE_Xplore

Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications

IEEE transactions on very large scale integration (VLSI) systems, 2016-01, Vol.24 (1), p.358-362

2016

Link zum Volltext
IEEE_Xplore

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

IEEE transactions on circuits and systems. II, Express briefs, 2014-04, Vol.61 (4), p.259-263

2014

Link zum Volltext
IEEE_Xplore

An All-Digital, [Formula Omitted]-Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop

IEEE journal of solid-state circuits, 2020-01, Vol.55 (7), p.1898

2020

Link zum Volltext

Verfügbarkeit prüfen

Analysis of Neutron-Induced Multibit-Upset Clusters in a 14-nm Flip-Flop Array

IEEE transactions on nuclear science, 2019-06, Vol.66 (6), p.918-925

2019

Link zum Volltext
IEEE_Xplore

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65nm CMOS

IEEE transactions on circuits and systems. I, Regular papers, 2016-04, Vol.63 (6), p.806

2016

Link zum Volltext

Verfügbarkeit prüfen

Automated Design For Yield Through Defect Tolerance

2020 IEEE 38th VLSI Test Symposium (VTS), 2020, p.1-6

2020

Link zum Volltext
IEEE_Xplore

Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization

2020 IEEE International Test Conference (ITC), 2020, p.1-10

2020

Link zum Volltext
IEEE_Xplore

Benchmarking of Standard-Cell Based Memories in the sub-VT Domain in 65-nm CMOS Technology

IEEE journal on emerging and selected topics in circuits and systems, 2011-06, Vol.1 (2), p.173

2011

Link zum Volltext

Verfügbarkeit prüfen

An All-Digital, V MAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop

IEEE solid-state circuits letters, 2019-09, Vol.2 (9), p.143-146

2019

Link zum Volltext
IEEE_Xplore

An All-Digital, VMAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019, p.1-4

2019

Link zum Volltext
IEEE_Xplore

1 – 25 von 64

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(20)
Mit Volltextzugriff
(62)

Publikationsform

Sprache

Englisch
(64)
Japanisch
(7)

Erscheinungsjahr

n.n

Thema

Engineering
(25)
Science & Technology
(25)
Technology
(25)
Engineering, Electrical & Electronic
(23)
Random Access Memory
(18)
Latches
(13)
Clocks
(12)
Cmos Integrated Circuits
(12)
Arrays
(11)
Circuits & Components
(11)
Electronics Engineering
(11)
Storage Media & Peripherals
(11)
Transistors
(11)
Computer Science
(10)
Electrical Engineering, Electronic Engineering, Information Engineering
(8)
Elektroteknik Och Elektronik
(8)
Engineering And Technology
(8)
Teknik
(8)
Tin
(8)
Computer Science, Hardware & Architecture
(7)

15 weitere anzeigen...

Weniger anzeigen...

Kollektion

IEEE Electronic Library (IEL)
(43)
Ingenta
(22)
Ebook Central Perpetual and DDA
(16)
eBooks on EBSCOhost
(16)
ACM Digital Library Complete
(3)
IngentaConnect Journals
(2)
EZB-FREE-00999 freely available EZB journals
(2)
Wiley Online Library Journals Frontfile Complete
(1)

3 weitere anzeigen...

Weniger anzeigen...

Menü

Weitere Dienste

Einstellungen

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and } Optimization

Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-On-Chip

Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling

Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS

A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS

A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS

Impact of body biasing on the retention time of gain-cell memories

Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation

A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications

Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

Benchmarking of Standard-Cell Based Memories in the Sub- V Domain in 65-nm CMOS Technology

An All-Digital, V} -Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop

Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

An All-Digital, [Formula Omitted]-Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop

Analysis of Neutron-Induced Multibit-Upset Clusters in a 14-nm Flip-Flop Array

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65nm CMOS

Automated Design For Yield Through Defect Tolerance

Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization

Benchmarking of Standard-Cell Based Memories in the sub-VT Domain in 65-nm CMOS Technology

An All-Digital, V MAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop

An All-Digital, VMAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop

Suchergebnisse filtern