UB Paderborn / Katalog / Suche / in CDI

1 – 25 von 585

Sortiert nach

Performance Impacts of Analog ReRAM Non-ideality on Neuromorphic Computing

IEEE transactions on electron devices, 2019-03, Vol.66 (3), p.1289-1295

2019

Volltextzugriff (PDF)

ReRAM-Based Pseudo-True Random Number Generator With High Throughput and Unpredictability Characteristics

IEEE transactions on electron devices, 2021-04, Vol.68 (4), p.1593-1597

2021

Volltextzugriff (PDF)

Asymmetric Interference Behavior in 3D NAND Cell and the Reverse Trend Induced by Undercut of Sacrificial Nitride Film

IEEE electron device letters, 2022-12, Vol.43 (12), p.1-1

2022

Volltextzugriff (PDF)

Electric Field Induced Nitride Trapped Charge Lateral Migration in a SONOS Flash Memory

IEEE electron device letters, 2017-01, Vol.38 (1), p.48-51

2017

Volltextzugriff (PDF)

A Novel SuperSteep Subthreshold Slope Dual-Channel FET Utilizing a Gate-Controlled Thyristor Mode-Induced Positive Feedback Current

IEEE transactions on electron devices, 2017-03, Vol.64 (3), p.1336-1342

2017

Volltextzugriff (PDF)

Poly-Silicon Trap Position and Pass Voltage Effects on RTN Amplitude in a Vertical NAND Flash Cell String

IEEE electron device letters, 2016-08, Vol.37 (8), p.998-1001

2016

Volltextzugriff (PDF)

Performance Enhancement of 3-D NAND Flash Featuring a Two-Step Dummy Wordline Program Waveform and Pair-Bitline Program Scheme

IEEE transactions on electron devices, 2020-01, Vol.67 (1), p.99-104

2020

Volltextzugriff (PDF)

Grain Boundary Trap-Induced Current Transient in a 3-D NAND Flash Cell String

IEEE transactions on electron devices, 2019-04, Vol.66 (4), p.1734-1740

2019

Volltextzugriff (PDF)

A high-efficiency, reliable multilevel hardware-accelerated annealer with in-memory spin coupling and complementary read algorithm

Japanese Journal of Applied Physics, 2023-04, Vol.62 (SC), p.SC1085

2023

Volltextzugriff (PDF)

Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D NAND Flash Memory Devices

IEEE transactions on electron devices, 2014-06, Vol.61 (6), p.2064-2070

2014

Volltextzugriff (PDF)

Characterization of nitride hole lateral transport in a charge trap flash memory by using a random telegraph signal method

Applied physics letters, 2017-07, Vol.111 (3)

2017

Volltextzugriff (PDF)

A Novel Varying-Bias Read Scheme for MLC and Wide Temperature Range TMO ReRAM

IEEE electron device letters, 2016-11, Vol.37 (11), p.1426-1429

2016

Volltextzugriff (PDF)

Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND

IEEE transactions on electron devices, 2016-03, Vol.63 (3), p.1047-1053

2016

Volltextzugriff (PDF)

Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations

IEEE journal of solid-state circuits, 2015-06, Vol.50 (6), p.1491-1501

2015

Volltextzugriff (PDF)

Ultra-High Bit Density 3D NAND Flash-Featuring-Assisted Gate Operation

IEEE electron device letters, 2015-10, Vol.36 (10), p.1015-1017

2015

Volltextzugriff (PDF)

A Study of Gate-Sensing and Channel-Sensing (GSCS) Transient Analysis Method-Part I: Fundamental Theory and Applications to Study of the Trapped Charge Vertical Location and Capture Efficiency of SONOS-Type Devices

IEEE transactions on electron devices, 2008-08, Vol.55 (8), p.2218-2228

2008

Volltextzugriff (PDF)

Studies of the reverse read method and second-bit effect of 2-bit/cell nitride-trapping device by quasi-two-dimensional model

IEEE transactions on electron devices, 2006-01, Vol.53 (1), p.119-125

2006

Volltextzugriff (PDF)

Physical Model of Field Enhancement and Edge Effects of FinFET Charge-Trapping NAND Flash Devices

IEEE transactions on electron devices, 2009-06, Vol.56 (6), p.1235-1242

2009

Volltextzugriff (PDF)

Cycling-Induced SET-Disturb Failure Time Degradation in a Resistive Switching Memory

IEEE electron device letters, 2015-02, Vol.36 (2), p.135-137

2015

Volltextzugriff (PDF)

A New String Decoding Scheme for Enhancing Array Block Efficiency of Vertical Gate Type (VG-Type) 3-D NAND

IEEE electron device letters, 2015-04, Vol.36 (4), p.330-332

2015

Volltextzugriff (PDF)

Future challenges of flash memory technologies

Microelectronic engineering, 2009-03, Vol.86 (3), p.283-286

2009

Volltextzugriff (PDF)

Numerical Simulation of Bottom Oxide Thickness Effect on Charge Retention in SONOS Flash Memory Cells

IEEE transactions on electron devices, 2007-01, Vol.54 (1), p.90-97

2007

Volltextzugriff (PDF)

A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device

2010 Symposium on VLSI Technology, 2010, p.131-132

2010

Volltextzugriff (PDF)

A Study of Gate-Sensing and Channel-Sensing (GSCS) Transient Analysis Method Part II: Study of the Intra-Nitride Behaviors and Reliability of SONOS-Type Devices

IEEE transactions on electron devices, 2008-08, Vol.55 (8), p.2229-2237

2008

Volltextzugriff (PDF)

Investigation of Electron and Hole Lateral Migration in Silicon Nitride and Data Pattern Effects on } Retention Loss in a Multilevel Charge Trap Flash Memory

IEEE transactions on electron devices, 2019-12, Vol.66 (12), p.5155-5161

2019

Volltextzugriff (PDF)

1 – 25 von 585

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(296)
Mit Volltextzugriff
(523)

Publikationsform

2 weitere anzeigen...

Weniger anzeigen...

Sprache

Erscheinungsjahr

n.n

Thema

Science & Technology
(358)
Technology
(274)
Engineering
(247)
Engineering, Electrical & Electronic
(243)
Physical Sciences
(134)
Physics
(126)
Physics, Applied
(98)
Flash Memory
(93)
Exact Sciences And Technology
(85)
Logic Gates
(84)
Applied Sciences
(74)
Electronics
(73)
Nonvolatile Memory
(71)
Tunneling
(70)
Three-Dimensional Displays
(69)
Semiconductor Electronics. Microelectronics. Optoelectronics. Solid State Devices
(67)
Life Sciences & Biomedicine
(64)
Electron Traps
(62)
Sonos Devices
(58)
Programming
(57)

15 weitere anzeigen...

Weniger anzeigen...

Neu hinzugefügt

... seit 7 Tagen
(1)
... seit 90 Tagen
(6)

Menü

Weitere Dienste

Einstellungen

Performance Impacts of Analog ReRAM Non-ideality on Neuromorphic Computing

ReRAM-Based Pseudo-True Random Number Generator With High Throughput and Unpredictability Characteristics

Asymmetric Interference Behavior in 3D NAND Cell and the Reverse Trend Induced by Undercut of Sacrificial Nitride Film

Electric Field Induced Nitride Trapped Charge Lateral Migration in a SONOS Flash Memory

A Novel SuperSteep Subthreshold Slope Dual-Channel FET Utilizing a Gate-Controlled Thyristor Mode-Induced Positive Feedback Current

Poly-Silicon Trap Position and Pass Voltage Effects on RTN Amplitude in a Vertical NAND Flash Cell String

Performance Enhancement of 3-D NAND Flash Featuring a Two-Step Dummy Wordline Program Waveform and Pair-Bitline Program Scheme

Grain Boundary Trap-Induced Current Transient in a 3-D NAND Flash Cell String

A high-efficiency, reliable multilevel hardware-accelerated annealer with in-memory spin coupling and complementary read algorithm

Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D NAND Flash Memory Devices

Characterization of nitride hole lateral transport in a charge trap flash memory by using a random telegraph signal method

A Novel Varying-Bias Read Scheme for MLC and Wide Temperature Range TMO ReRAM

Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND

Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations

Ultra-High Bit Density 3D NAND Flash-Featuring-Assisted Gate Operation

A Study of Gate-Sensing and Channel-Sensing (GSCS) Transient Analysis Method-Part I: Fundamental Theory and Applications to Study of the Trapped Charge Vertical Location and Capture Efficiency of SONOS-Type Devices

Studies of the reverse read method and second-bit effect of 2-bit/cell nitride-trapping device by quasi-two-dimensional model

Physical Model of Field Enhancement and Edge Effects of FinFET Charge-Trapping NAND Flash Devices

Cycling-Induced SET-Disturb Failure Time Degradation in a Resistive Switching Memory

A New String Decoding Scheme for Enhancing Array Block Efficiency of Vertical Gate Type (VG-Type) 3-D NAND

Future challenges of flash memory technologies

Numerical Simulation of Bottom Oxide Thickness Effect on Charge Retention in SONOS Flash Memory Cells

A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device

A Study of Gate-Sensing and Channel-Sensing (GSCS) Transient Analysis Method Part II: Study of the Intra-Nitride Behaviors and Reliability of SONOS-Type Devices

Investigation of Electron and Hole Lateral Migration in Silicon Nitride and Data Pattern Effects on } Retention Loss in a Multilevel Charge Trap Flash Memory

Suchergebnisse filtern