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Heterogeneous Monolithic 3-D IC Designs: Challenges, EDA Solutions, and Power, Performance, Cost Tradeoffs

IEEE transactions on very large scale integration (VLSI) systems, 2024-03, Vol.32 (3), p.413-421

2024

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Prediction of changes in the pumping speed characteristics of dry pumps with the geometry of the conduit

Journal of the Korean Physical Society, 2022, 80(4), , pp.337-346

2022

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Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools

2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2016, p.1-8

2016

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Performance and Thermal-Aware Steiner Routing for 3-D Stacked ICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2009-09, Vol.28 (9), p.1373-1386

2009

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Sidewall Slope Control of InP Via Holes for 3D Integration

Micromachines (Basel), 2021-01, Vol.12 (1), p.89

2021

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Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs

2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2016, p.1-7

2016

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Design of 3D Integrated Circuits and Systems

1, 2018

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Shrunk-2-D: A Physical Design Methodology to Build Commercial-Quality Monolithic 3-D ICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-10, Vol.36 (10), p.1716-1724

2017

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Block-level 3-D Global Routing With an Application to 3-D Packaging

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-10, Vol.25 (10), p.2248-2257

2006

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FAFNIR: Accelerating Sparse Gathering by Using Efficient Near-Memory Intelligent Reduction

2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2021, p.908-920

2021

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Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-04, Vol.34 (4), p.540-553

2015

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TSV-Based 3-D ICs: Design Methods and Tools

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-10, Vol.36 (10), p.1593-1619

2017

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Decoupling-Capacitor Planning and Sizing for Noise and Leakage Reduction

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-11, Vol.26 (11), p.2023-2034

2007

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Electrical Coupling of Monolithic 3-D Inverters

IEEE transactions on electron devices, 2016-08, Vol.63 (8), p.3346-3349

2016

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Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout

IEEE transactions on very large scale integration (VLSI) systems, 2013-05, Vol.21 (5), p.862-874

2013

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Edge separability-based circuit clustering with application to multilevel circuit partitioning

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-03, Vol.23 (3), p.346-357

2004

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TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2014-09, Vol.33 (9), p.1384-1395

2014

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Antiferroelectric negative capacitance from a structural phase transition in zirconia

Nature communications, 2022-03, Vol.13 (1), p.1228-1228, Article 1228

2022

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Traffic: a novel geometric algorithm for fast wire-optimized floorplanning

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-06, Vol.25 (6), p.1075-1086

2006

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Exploiting Die-to-Die Thermal Coupling in 3-D IC Placement

IEEE transactions on very large scale integration (VLSI) systems, 2014-10, Vol.22 (10), p.2145-2155

2014

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Design and CAD methodologies for low power gate-level monolithic 3D ICs

2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2014, p.171-176

2014

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Ultrahigh Density Logic Designs Using Monolithic 3-D Integration

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-12, Vol.32 (12), p.1892-1905

2013

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Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling

IEEE transactions on computer-aided design of integrated circuits and systems, 2014-12, Vol.33 (12), p.1900-1913

2014

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TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-08, Vol.31 (8), p.1194-1207

2012

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Evaluating Chip-Level Impact of Cu/Low- \kappa Performance Degradation on Circuit Performance at Future Technology Nodes

IEEE transactions on electron devices, 2015-03, Vol.62 (3), p.940-946

2015

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Heterogeneous Monolithic 3-D IC Designs: Challenges, EDA Solutions, and Power, Performance, Cost Tradeoffs

Prediction of changes in the pumping speed characteristics of dry pumps with the geometry of the conduit

Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools

Performance and Thermal-Aware Steiner Routing for 3-D Stacked ICs

Sidewall Slope Control of InP Via Holes for 3D Integration

Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs

Design of 3D Integrated Circuits and Systems

Shrunk-2-D: A Physical Design Methodology to Build Commercial-Quality Monolithic 3-D ICs

Block-level 3-D Global Routing With an Application to 3-D Packaging

FAFNIR: Accelerating Sparse Gathering by Using Efficient Near-Memory Intelligent Reduction

Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs

TSV-Based 3-D ICs: Design Methods and Tools

Decoupling-Capacitor Planning and Sizing for Noise and Leakage Reduction

Electrical Coupling of Monolithic 3-D Inverters

Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout

Edge separability-based circuit clustering with application to multilevel circuit partitioning

TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs

Antiferroelectric negative capacitance from a structural phase transition in zirconia

Traffic: a novel geometric algorithm for fast wire-optimized floorplanning

Exploiting Die-to-Die Thermal Coupling in 3-D IC Placement

Design and CAD methodologies for low power gate-level monolithic 3D ICs

Ultrahigh Density Logic Designs Using Monolithic 3-D Integration

Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling

TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC

Evaluating Chip-Level Impact of Cu/Low- \kappa Performance Degradation on Circuit Performance at Future Technology Nodes

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