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Baf-mediated transcriptional regulation of teashirt is essential for the development of neural progenitor cell lineages

Experimental & molecular medicine, 2024-02, Vol.56 (2), p.422-440

2024

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Low Cost Ternary Content Addressable Memory Using Adaptive Matchline Discharging Scheme

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, p.1-4

2018

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Temporally Robust Eye Movements through Task Priming and Self-referential Stimuli

Scientific reports, 2017-08, Vol.7 (1), p.7257-11, Article 7257

2017

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A 28-nm 50.1-TOPS/W P-8T SRAM Compute-In-Memory Macro Design With BL Charge-Sharing-Based In-SRAM DAC/ADC Operations

IEEE journal of solid-state circuits, 2024-06, Vol.59 (6), p.1926-1937

2024

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The peripheral and central mechanisms underlying itch

BMB reports, 2016-09, Vol.49 (9), p.474-487

2016

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A 2941-TOPS/W Charge-Domain 10T SRAM Compute-in-Memory for Ternary Neural Network

IEEE transactions on circuits and systems. I, Regular papers, 2023-05, Vol.70 (5), p.1-13

2023

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IEEE_Xplore

A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line Discharge

IEEE journal of solid-state circuits, 2021-08, Vol.56 (8), p.2574-2584

2021

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IEEE_Xplore

Low Area and Low Power Threshold Implementation Design Technique for AES S-Box

IEEE transactions on circuits and systems. II, Express briefs, 2023-03, Vol.70 (3), p.1169-1173

2023

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IEEE_Xplore

Low-Cost 7T-SRAM Compute-in-Memory Design Based on Bit-Line Charge-Sharing Based Analog-to-Digital Conversion

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2022, p.1-8

2022

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IEEE_Xplore

An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance

IEEE journal of solid-state circuits, 2000-03, Vol.35 (3), p.377-384

2000

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IEEE_Xplore

Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision

2020 57th ACM/IEEE Design Automation Conference (DAC), 2020, p.1-6

2020

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A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing

Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, 2022, p.1-6

2022

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A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

IEEE journal of solid-state circuits, 2002-05, Vol.37 (5), p.536-542

2002

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IEEE_Xplore

A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration

2021 58th ACM/IEEE Design Automation Conference (DAC), 2021, p.739-744

2021

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Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver

IEEE journal of solid-state circuits, 2003-01, Vol.38 (1), p.43-53

2003

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IEEE_Xplore

Low Cost Ternary Content Addressable Memory Based on Early Termination Precharge Scheme

2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, p.1-4

2019

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IEEE_Xplore

The peripheral and central mechanisms underlying itch

BMB Reports, 2016, 49(9), , pp.474-487

2016

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Content addressable memory based binarized neural network accelerator using time-domain signal processing

Proceedings of the 55th Annual Design Automation Conference, 2018, p.1-6

2018

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A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL

IEEE journal of solid-state circuits, 1997-05, Vol.32 (5), p.691-700

1997

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IEEE_Xplore

Novel traffic measurement methodology for high precision applications awareness in multi-gigabit networks

Lecture notes in computer science, 2006, p.63-72

2006

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A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique

IEEE journal of solid-state circuits, 2001-05, Vol.36 (5), p.800-809

2001

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IEEE_Xplore

Comparison frequency doubling and charge pump matching techniques for dual-band /spl Delta//spl Sigma/ fractional-N frequency synthesizer

IEEE journal of solid-state circuits, 2005-11, Vol.40 (11), p.2228-2236

2005

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IEEE_Xplore

Machine-Learning Based Automatic and Real-time Detection of Mouse Scratching Behaviors

Experimental Neurobiology, 2019, 28(1), , pp.54-61

2019

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A CMOS serial link for fully duplexed data communication

IEEE journal of solid-state circuits, 1995-04, Vol.30 (4), p.353-364

1995

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IEEE_Xplore

Wire-speed application flow generation in hardware platform for multi-gigabit traffic monitoring

NOMS 2008 - 2008 IEEE Network Operations and Management Symposium, 2008, p.184-191

2008

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IEEE_Xplore

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Baf-mediated transcriptional regulation of teashirt is essential for the development of neural progenitor cell lineages

Low Cost Ternary Content Addressable Memory Using Adaptive Matchline Discharging Scheme

Temporally Robust Eye Movements through Task Priming and Self-referential Stimuli

A 28-nm 50.1-TOPS/W P-8T SRAM Compute-In-Memory Macro Design With BL Charge-Sharing-Based In-SRAM DAC/ADC Operations

The peripheral and central mechanisms underlying itch

A 2941-TOPS/W Charge-Domain 10T SRAM Compute-in-Memory for Ternary Neural Network

A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line Discharge

Low Area and Low Power Threshold Implementation Design Technique for AES S-Box

Low-Cost 7T-SRAM Compute-in-Memory Design Based on Bit-Line Charge-Sharing Based Analog-to-Digital Conversion

An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance

Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision

A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing

A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration

Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver

Low Cost Ternary Content Addressable Memory Based on Early Termination Precharge Scheme

The peripheral and central mechanisms underlying itch

Content addressable memory based binarized neural network accelerator using time-domain signal processing

A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL

Novel traffic measurement methodology for high precision applications awareness in multi-gigabit networks

A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique

Comparison frequency doubling and charge pump matching techniques for dual-band /spl Delta//spl Sigma/ fractional-N frequency synthesizer

Machine-Learning Based Automatic and Real-time Detection of Mouse Scratching Behaviors

A CMOS serial link for fully duplexed data communication

Wire-speed application flow generation in hardware platform for multi-gigabit traffic monitoring

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