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A transparent conducting oxide as an efficient middle electrode for flexible organic tandem solar cells

Solar energy materials and solar cells, 2010-03, Vol.94 (3), p.542-546

2010

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A 20-GHZ phase-locked loop for 40-Gb/s serializing transmitter in 0.13-μm CMOS

IEEE journal of solid-state circuits, 2006-04, Vol.41 (4), p.899-908

2006

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A Single-Pair Serial Link for Mobile Displays With Clock Edge Modulation Scheme

IEEE journal of solid-state circuits, 2007-09, Vol.42 (9), p.2012-2020

2007

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IEEE_Xplore

A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

IEEE journal of solid-state circuits, 2002-12, Vol.37 (12), p.1822-1830

2002

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A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique

IEEE journal of solid-state circuits, 2005-11, Vol.40 (11), p.2148-2158

2005

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IEEE_Xplore

Photopatterning of Cell-Adhesive-Modified Poly(ethyleneimine) for Guided Neuronal Growth

Langmuir, 2011-03, Vol.27 (6), p.2717-2722

2011

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A 2.5-10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characteristic stabilization

IEEE journal of solid-state circuits, 2003-11, Vol.38 (11), p.1821-1829

2003

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IEEE_Xplore

A 5 Gb/s 0.25 mu m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

Digest of technical papers - IEEE International Solid-State Circuits Conference, 2002-01, p.206-207+474

2002

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A 3-mW, 270-Mbps, Clock-Edge Modulated Serial Link for Mobile Displays

2005 IEEE Asian Solid-State Circuits Conference, 2005, p.45-48

2005

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IEEE_Xplore

Design Optimization of On-Chip Inductive Peaking Structures for 0.13- mu hbox m CMOS 40-Gb/s Transmitter Circuits

IEEE transactions on circuits and systems. I, Regular papers, 2009-12, Vol.56 (12), p.2544-2555

2009

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Design Optimization of On-Chip Inductive Peaking Structures for 0.13- \mu} CMOS 40-Gb/s Transmitter Circuits

IEEE transactions on circuits and systems. I, Regular papers, 2009-12, Vol.56 (12), p.2544-2555

2009

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IEEE_Xplore

Facile photopatterning of polyfluorene for patterned neuronal networks

Soft matter, 2011-01, Vol.7 (21), p.10025-10031

2011

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A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-mum CMOS

IEEE journal of solid-state circuits, 2006-04, Vol.41 (4), p.899-908

2006

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A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-/spl mu/m CMOS

IEEE journal of solid-state circuits, 2006-04, Vol.41 (4), p.899-908

2006

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IEEE_Xplore

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-[micro]m CMOS

IEEE journal of solid-state circuits, 2006-04, Vol.41 (4), p.899

2006

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A Bandpass ΔΣ Interface IC for Sacrificial Bulk Micromachined Inertial Sensors

2006 IEEE Asian Solid-State Circuits Conference, 2006, p.439-442

2006

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IEEE_Xplore

A 5-Gb/s 0.25-/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

IEEE journal of solid-state circuits, 2002-12, Vol.37 (12), p.1822-1830

2002

Link zum Volltext
IEEE_Xplore

A 5-Gb/s 0.25-mum CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

IEEE journal of solid-state circuits, 2002-12, Vol.37 (12), p.1822-1830

2002

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A 5-Gb/s 0.25-[micro]m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

IEEE journal of solid-state circuits, 2002-12, Vol.37 (12), p.1822

2002

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A 2.5-10Gb/s CMOS transceiver with alternating edge sampling phase detection for loop characteristic stabilization

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC, 2003, p.76-479 vol.1

2003

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IEEE_Xplore

Circuit techniques for a 40Gb/s transmitter in 0.13/spl mu/m CMOS

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.150-589 Vol. 1

2005

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IEEE_Xplore

A fully integrated 0.13 /spl mu/m CMOS 10 Gb Ethernet transceiver with XAUI interface

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519), 2004, p.170-520 Vol.1

2004

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IEEE_Xplore

A fully integrated 0.13μm CMOS 10Gb ethernet transceiver with XAUI interface

First edition, 2004

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Inhibitory Effect of Elaeagnus umbellata Fractions on Melanogenesis in α-MSH-Stimulated B16-F10 Melanoma Cells

Molecules (Basel, Switzerland), 2021-03, Vol.26 (5), p.1308

2021

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Oncological and anorectal functional outcomes of robot-assisted intersphincteric resection in lower rectal cancer, particularly the extent of sphincter resection and sphincter saving

Surgical endoscopy, 2020-05, Vol.34 (5), p.2082-2094

2020

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A transparent conducting oxide as an efficient middle electrode for flexible organic tandem solar cells

A 20-GHZ phase-locked loop for 40-Gb/s serializing transmitter in 0.13-μm CMOS

A Single-Pair Serial Link for Mobile Displays With Clock Edge Modulation Scheme

A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique

Photopatterning of Cell-Adhesive-Modified Poly(ethyleneimine) for Guided Neuronal Growth

A 2.5-10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characteristic stabilization

A 5 Gb/s 0.25 mu m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

A 3-mW, 270-Mbps, Clock-Edge Modulated Serial Link for Mobile Displays

Design Optimization of On-Chip Inductive Peaking Structures for 0.13- mu hbox m CMOS 40-Gb/s Transmitter Circuits

Design Optimization of On-Chip Inductive Peaking Structures for 0.13- \mu} CMOS 40-Gb/s Transmitter Circuits

Facile photopatterning of polyfluorene for patterned neuronal networks

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-mum CMOS

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-/spl mu/m CMOS

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-[micro]m CMOS

A Bandpass ΔΣ Interface IC for Sacrificial Bulk Micromachined Inertial Sensors

A 5-Gb/s 0.25-/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

A 5-Gb/s 0.25-mum CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

A 5-Gb/s 0.25-[micro]m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

A 2.5-10Gb/s CMOS transceiver with alternating edge sampling phase detection for loop characteristic stabilization

Circuit techniques for a 40Gb/s transmitter in 0.13/spl mu/m CMOS

A fully integrated 0.13 /spl mu/m CMOS 10 Gb Ethernet transceiver with XAUI interface

A fully integrated 0.13μm CMOS 10Gb ethernet transceiver with XAUI interface

Inhibitory Effect of Elaeagnus umbellata Fractions on Melanogenesis in α-MSH-Stimulated B16-F10 Melanoma Cells

Oncological and anorectal functional outcomes of robot-assisted intersphincteric resection in lower rectal cancer, particularly the extent of sphincter resection and sphincter saving

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