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Attaché: towards ideal memory compression by mitigating metadata bandwidth overheads

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2018, p.326-338

2018

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Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013, p.48-59

2013

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A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling

IEEE journal of solid-state circuits, 2022-01, Vol.57 (1), p.182-197

2022

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Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-12, Vol.39 (12), p.4635-4644

2020

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RaPiD: AI accelerator for ultra-low precision training and inference

2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), 2021, p.153-166

2021

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A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, p.1-2

2023

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14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.254-256

2024

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A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter

IEEE journal of solid-state circuits, 2006-01, Vol.41 (1), p.127-134

2006

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Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor

2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2017, p.15-26

2017

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An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme

IEEE journal of solid-state circuits, 2007-01, Vol.42 (1), p.193-200

2007

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Mixed-Signal Dot-Product Processor with Switched-Capacitors for Machine Learning

2024 International Conference on Electronics, Information, and Communication (ICEIC), 2024, p.1-4

2024

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A Second Order Mixed-Mode Charge Pump Scheme for Low Phase/Duty Error and Low Power Consumption

IEICE transactions on electronics, 2007-01, Vol.E90-C (1), p.208-211

2007

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A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.458-627

2008

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Low-power dynamic termination scheme using NMOS diode clamping

IEEE journal of solid-state circuits, 1999-08, Vol.34 (8), p.1171-1175

1999

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OpenCAPI Memory Interface Signal Integrity Study for High-Speed DDR5 Differential DIMM Channel with Standard Loss FR-4 Material and SNIA SFF-TA-1002 Connector

2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019, p.1200-1207

2019

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Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC

IEEE journal of solid-state circuits, 2024-10, p.1-16

2024

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Session 25 Overview: DRAM

2021 IEEE International Solid-State Circuits Conference (ISSCC), 2021, Vol.64, p.342-343

2021

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Vref optimization in DDR4 RDIMMs for improved timing margins

2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2014, p.73-76

2014

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8-bit-resolution, 360- mu s write time nonvolatile analog memory based on Differentially Balanced Constant-Tunneling-Current Scheme (DBCS)

IEEE journal of solid-state circuits, 1998-11, Vol.33 (11), p.1758-1762

1998

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A 20GB/s 256MB DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.470-471 Vol. 1

2005

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A 1.4 Gb/s DLL using 2nd order charge-pump scheme with low phase/duty error for high-speed DRAM application

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519), 2004, p.212-523 Vol.1

First edition, 2004

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9.1 A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.144-146

2021

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A true nonvolatile analog memory cell using coupling-charge balancing

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC, 1996, p.268-269

1996

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A 512-Mb DDR3 SDRAM Prototype With $C_IO$ Minimization and Self-Calibration Techniques

IEEE journal of solid-state circuits, 2006-04, Vol.41 (4), p.831-838

2006

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Design of the IBM Blue Gene/Q Compute chip

IBM journal of research and development, 2013-01, Vol.57 (1/2), p.1-1:13

IBM Blue Gene team

2013

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Attaché: towards ideal memory compression by mitigating metadata bandwidth overheads

Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling

Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem

RaPiD: AI accelerator for ultra-low precision training and inference

A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC

A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter

Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor

An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme

Mixed-Signal Dot-Product Processor with Switched-Capacitors for Machine Learning

A Second Order Mixed-Mode Charge Pump Scheme for Low Phase/Duty Error and Low Power Consumption

A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator

Low-power dynamic termination scheme using NMOS diode clamping

OpenCAPI Memory Interface Signal Integrity Study for High-Speed DDR5 Differential DIMM Channel with Standard Loss FR-4 Material and SNIA SFF-TA-1002 Connector

Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC

Session 25 Overview: DRAM

Vref optimization in DDR4 RDIMMs for improved timing margins

8-bit-resolution, 360- mu s write time nonvolatile analog memory based on Differentially Balanced Constant-Tunneling-Current Scheme (DBCS)

A 20GB/s 256MB DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter

A 1.4 Gb/s DLL using 2nd order charge-pump scheme with low phase/duty error for high-speed DRAM application

9.1 A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling

A true nonvolatile analog memory cell using coupling-charge balancing

A 512-Mb DDR3 SDRAM Prototype With $C_IO$ Minimization and Self-Calibration Techniques

Design of the IBM Blue Gene/Q Compute chip

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