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Analysis of the parasitic S/D resistance in multiple-gate FETs

IEEE transactions on electron devices, 2005-06, Vol.52 (6), p.1132-1140

2005

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Dual- k Spacer Device Architecture for the Improvement of Performance of Silicon n-Channel Tunnel FETs

IEEE transactions on electron devices, 2010-10, Vol.57 (10), p.2410-2417

2010

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Bulk Planar Junctionless Transistor (BPJLT): An Attractive Device Alternative for Scaling

IEEE electron device letters, 2011-03, Vol.32 (3), p.261-263

2011

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Extraction of the Top and Sidewall Mobility in FinFETs and the Impact of Fin-Patterning Processes and Gate Dielectrics on Mobility

IEEE transactions on electron devices, 2007-05, Vol.54 (5), p.1177-1184

2007

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Enhanced Electrostatic Integrity of Short-Channel Junctionless Transistor With High- \kappa Spacers

IEEE electron device letters, 2011-10, Vol.32 (10), p.1325-1327

2011

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Effect of Band-to-Band Tunneling on Junctionless Transistors

IEEE transactions on electron devices, 2012-04, Vol.59 (4), p.1023-1029

2012

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Reduction of the anomalous VT behavior in MOSFETs with high- κ/metal gate stacks

Microelectronic engineering, 2007-09, Vol.84 (9), p.1882-1885

2007

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Silicon tunneling field-effect transistors with tunneling in line with the gate field

IEEE electron device letters, 2013-02, Vol.34 (2), p.154-156

2013

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Aluminum Oxide Deposited by Pulsed-DC Reactive Sputtering for Crystalline Silicon Surface Passivation

IEEE journal of photovoltaics, 2013-07, Vol.3 (3), p.930-935

2013

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Modified STC Correction Procedure for Assessing PV Module Degradation in Field Surveys

2017 IEEE 44th Photovoltaic Specialist Conference (PVSC), 2017, p.1995-1999

2017

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Dopant diffusion during rapid thermal oxidation

Solid-state electronics, 2000-05, Vol.44 (5), p.831-835

2000

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Optimization of ICP-CVD silicon nitride for Si solar cell passivation

2012 38th IEEE Photovoltaic Specialists Conference, 2012, p.001102-001104

2012

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Integration challenges for multi-gate devices

2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005, 2005, p.187-194

2005

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Optimization of n-channel tunnel FET for the sub-22nm gate length regime

2008 Device Research Conference, 2008, p.77-78

2008

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Investigation of nature of UV induced negative charge in AI2O3 films

2016 3rd International Conference on Emerging Electronics (ICEE), 2016, p.1-4

2016

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Applications of Ni-based silicides to 45 nm CMOS and Beyond

MRS proceedings, 2004, Vol.810, Article C2.1

2004

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Dopant profiling in NixSi1−x gates with secondary-ion-mass spectroscopy

Journal of vacuum science & technology. B, Microelectronics and nanometer structures processing, measurement and phenomena, 2006-01, Vol.24 (1), p.399-403

2006

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Optimization of hetero junction n-channel tunnel FET with high-k spacers

2009 2nd International Workshop on Electron Devices and Semiconductor Technology, 2009, p.1-6

2009

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Multilayer Graphene as Charge Storage Layer in Floating Gate Flash Memory

2012 4th IEEE International Memory Workshop, 2012, p.1-4

2012

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Si Tunneling Field Effect Transistor with Tunnelling In-Line with the Gate Field

2012 International Silicon-Germanium Technology and Device Meeting (ISTDM), 2012, p.1-2

2012

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Bottom-up method for work function tuning in high-k/metal gate stacks in advanced CMOS technologies

2011 11th IEEE International Conference on Nanotechnology, 2011, p.269-273

2011

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Experimental evidence of short-channel electron mobility degradation caused by interface charges located at the gate-edge of triple-gate FinFETs

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, 2006, p.72-74

2006

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Dopant profiling in Ni x Si 1 − x gates with secondary-ion-mass spectroscopy

Journal of vacuum science & technology. B, Microelectronics and nanometer structures processing, measurement and phenomena, 2006-01, Vol.24 (1), p.399-403

2006

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GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO/sub 2/TiN FinFET devices

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest, 2005, p.725-728

2005

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MUGFET - alternative transistor architecture for 32 nm CMOS generation

2006 International Workshop on Junction Technology, 2006, p.1-1

2006

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Analysis of the parasitic S/D resistance in multiple-gate FETs

Dual- k Spacer Device Architecture for the Improvement of Performance of Silicon n-Channel Tunnel FETs

Bulk Planar Junctionless Transistor (BPJLT): An Attractive Device Alternative for Scaling

Extraction of the Top and Sidewall Mobility in FinFETs and the Impact of Fin-Patterning Processes and Gate Dielectrics on Mobility

Enhanced Electrostatic Integrity of Short-Channel Junctionless Transistor With High- \kappa Spacers

Effect of Band-to-Band Tunneling on Junctionless Transistors

Reduction of the anomalous VT behavior in MOSFETs with high- κ/metal gate stacks

Silicon tunneling field-effect transistors with tunneling in line with the gate field

Aluminum Oxide Deposited by Pulsed-DC Reactive Sputtering for Crystalline Silicon Surface Passivation

Modified STC Correction Procedure for Assessing PV Module Degradation in Field Surveys

Dopant diffusion during rapid thermal oxidation

Optimization of ICP-CVD silicon nitride for Si solar cell passivation

Integration challenges for multi-gate devices

Optimization of n-channel tunnel FET for the sub-22nm gate length regime

Investigation of nature of UV induced negative charge in AI2O3 films

Applications of Ni-based silicides to 45 nm CMOS and Beyond

Dopant profiling in NixSi1−x gates with secondary-ion-mass spectroscopy

Optimization of hetero junction n-channel tunnel FET with high-k spacers

Multilayer Graphene as Charge Storage Layer in Floating Gate Flash Memory

Si Tunneling Field Effect Transistor with Tunnelling In-Line with the Gate Field

Bottom-up method for work function tuning in high-k/metal gate stacks in advanced CMOS technologies

Experimental evidence of short-channel electron mobility degradation caused by interface charges located at the gate-edge of triple-gate FinFETs

Dopant profiling in Ni x Si 1 − x gates with secondary-ion-mass spectroscopy

GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO/sub 2/TiN FinFET devices

MUGFET - alternative transistor architecture for 32 nm CMOS generation

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