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Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector

IEEE journal of solid-state circuits, 2022-02, Vol.57 (2), p.573-585

2022

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A 1.05-to-3.2 GHz All-Digital PLL for DDR5 Registering Clock Driver With a Self-Biased Supply-Noise-Compensating Ring DCO

IEEE transactions on circuits and systems. II, Express briefs, 2022-03, Vol.69 (3), p.759-763

2022

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A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration

IEEE journal of solid-state circuits, 2021-08, Vol.56 (8), p.2525-2538

2021

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A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS

IEEE transactions on very large scale integration (VLSI) systems, 2020-05, Vol.28 (5), p.1099-1106

2020

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A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation

IEEE transactions on very large scale integration (VLSI) systems, 2020-12, Vol.28 (12), p.2708-2720

2020

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A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection

IEEE transactions on circuits and systems. I, Regular papers, 2018-09, Vol.65 (9), p.2691-2702

2018

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A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response

IEEE transactions on circuits and systems. II, Express briefs, 2019-12, Vol.66 (12), p.1932-1936

2019

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A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation

IEEE transactions on circuits and systems. II, Express briefs, 2020-10, Vol.67 (10), p.1735-1739

2020

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An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter

IEEE transactions on circuits and systems. II, Express briefs, 2018-12, Vol.65 (12), p.1819-1823

2018

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0.76-mW/pF/GHz, 7-GHz Quadrature Resonant Clock With Frequency Tuning Capacitor and Amplitude Control Feedback Loop

IEEE transactions on circuits and systems. II, Express briefs, 2021-01, Vol.68 (1), p.136-140

2021

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A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces

IEEE transactions on circuits and systems. II, Express briefs, 2020-10, Vol.67 (10), p.1814-1818

2020

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A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver

IEEE transactions on circuits and systems. II, Express briefs, 2019-12, Vol.66 (12), p.1927-1931

2019

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A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS

2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023, p.410-412

2023

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Reference Spur Reduction Techniques for a Phase-Locked Loop

IEEE access, 2019, Vol.7, p.38035-38043

2019

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25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections

IEEE transactions on circuits and systems. II, Express briefs, 2018-10, Vol.65 (10), p.1395-1399

2018

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A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS

IEEE access, 2021, Vol.9, p.156789-156798

2021

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A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), 2015, p.384-387

2015

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A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology

IEEE journal of solid-state circuits, 2019-10, Vol.54 (10), p.2812-2822

2019

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0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021, p.475-478

2021

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A 68.7-fJ/b/mm 375-GB/s/mm Single-Ended PAM-4 Interface with Per-Pin Training Sequence for the Next-Generation HBM Controller

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.150-151

2022

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A 3×12-Gb/s 1.26-pJ/b Single-Ended PAM-3 Transmitter With Crosstalk Cancellation Technique in 28-nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2024-08, p.1-1

2024

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A −247.1 dB FoM, −77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), 2022, p.249-252

2022

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A 64-Gb/s Ground-Referenced Signaling PAM-4 Transmitter with Switched-Capacitor Charge Pump Driver

2022 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2022, p.511-513

2022

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A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler

2020 IEEE Symposium on VLSI Circuits, 2020, p.1-2

2020

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A theoretical analysis of phase shift in pulse injection-locked oscillators

2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, p.1662-1665

2016

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Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector

A 1.05-to-3.2 GHz All-Digital PLL for DDR5 Registering Clock Driver With a Self-Biased Supply-Noise-Compensating Ring DCO

A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration

A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS

A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation

A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection

A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response

A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation

An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter

0.76-mW/pF/GHz, 7-GHz Quadrature Resonant Clock With Frequency Tuning Capacitor and Amplitude Control Feedback Loop

A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces

A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver

A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS

Reference Spur Reduction Techniques for a Phase-Locked Loop

25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections

A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection

A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology

0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link

A 68.7-fJ/b/mm 375-GB/s/mm Single-Ended PAM-4 Interface with Per-Pin Training Sequence for the Next-Generation HBM Controller

A 3×12-Gb/s 1.26-pJ/b Single-Ended PAM-3 Transmitter With Crosstalk Cancellation Technique in 28-nm CMOS

A −247.1 dB FoM, −77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration

A 64-Gb/s Ground-Referenced Signaling PAM-4 Transmitter with Switched-Capacitor Charge Pump Driver

A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler

A theoretical analysis of phase shift in pulse injection-locked oscillators

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