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Design and Optimization of Triple-k Spacer Structure in Two-Stack Nanosheet FET From OFF-State Leakage Perspective
IEEE transactions on electron devices, 2020-03, Vol.67 (3), p.1317-1322
2020
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Floating Fin Shaped Stacked Nanosheet MOSFET for Low Power Logic Application
IEEE journal of the Electron Devices Society, 2023-01, Vol.11, p.1-1
2023
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Efficient Convolutional Processing of Spiking Neural Network With Weight-Sharing Filters
IEEE electron device letters, 2023-06, Vol.44 (6), p.1007-1010
2023
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Comprehensive TCAD-Based Validation of Interface Trap-Assisted Ferroelectric Polarization in Ferroelectric-Gate Field-Effect Transistor Memory
IEEE transactions on electron devices, 2022-03, Vol.69 (3), p.1048-1053
2022
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Investigation of Device Performance for Fin Angle Optimization in FinFET and Gate-All-Around FETs for 3 nm-Node and Beyond
IEEE transactions on electron devices, 2022-04, Vol.69 (4), p.2088-2093
2022
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Investigation of Electrical Characteristic Behavior Induced by Channel-Release Process in Stacked Nanosheet Gate-All-Around MOSFETs
IEEE transactions on electron devices, 2020-06, Vol.67 (6), p.2648-2652
2020
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Novel Dual Liner Process for Side-Shielded Forksheet Device With Superior Design Margin
IEEE transactions on electron devices, 2022-05, Vol.69 (5), p.2232-2235
2022
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Investigation of Sidewall High-k Interfacial Layer Effect in Gate-All-Around Structure
IEEE transactions on electron devices, 2020-04, Vol.67 (4), p.1-5
2020
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Ferroelectric Field-Effect Transistor Synaptic Device With Hafnium-Silicate Interlayer
IEEE electron device letters, 2023-12, Vol.44 (12), p.1955-1958
2023
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Double-Gated Ferroelectric-Gate Field-Effect-Transistor for Processing in Memory
IEEE electron device letters, 2021-11, Vol.42 (11), p.1607-1610
2021
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Spiking Neural Network With Weight-Sharing Synaptic Array for Multi-input Processing
IEEE electron device letters, 2022-10, Vol.43 (10), p.1657-1660
2022
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Surface Ge-rich p-type SiGe channel tunnel field-effect transistor fabricated by local condensation technique
Solid-state electronics, 2020-02, Vol.164, p.107701, Article 107701
2020
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Investigation on Variability of Ferroelectric-Gate Field-Effect Transistor Memory by Random Spatial Distribution of Interface Trap
IEEE transactions on nanotechnology, 2022, Vol.21, p.534-538
2022
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Negative Capacitance Effect on MOS Structure: Influence of Electric Field Variation
IEEE transactions on nanotechnology, 2020, Vol.19, p.168-171
2020
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Analysis on Endurance Characteristics of Ferroelectric Memory Device
2022 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2022, p.630-633
2022
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Accurate Effective Width Extraction Methods for Sub-lOnm Multi-Gate MOSFETs through Capacitance Measurement
2019 Electron Devices Technology and Manufacturing Conference (EDTM), 2019, p.115-117
2019
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Novel Stacked Floating Fin Structure Gate-All-Around Field-Effect Transistor for Design and Power Optimization
2019 Electron Devices Technology and Manufacturing Conference (EDTM), 2019, p.136-138
2019
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Analysis on Fully Depleted Negative Capacitance Field-Effect Transistor (NCFET) Based on Electrostatic Potential Difference
2019 Electron Devices Technology and Manufacturing Conference (EDTM), 2019, p.422-424
2019
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