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A 0.007 mm 2 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2021-09, Vol.68 (9), p.3088-3092

2021

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A 0.007 mm2 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2021-09, Vol.68 (9), p.3088-3092

2021

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A 0.016 mV/mA Cross-Regulation 5-Output SIMO DC-DC Buck Converter Using Output-Voltage-Aware Charge Control Scheme

IEEE transactions on power electronics, 2018-11, Vol.33 (11), p.9619-9630

2018

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A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing

IEEE journal of solid-state circuits, 2008-02, Vol.43 (2), p.518-529

2008

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0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization

IEEE journal of solid-state circuits, 2016-06, Vol.51 (6), p.1487-1498

2016

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A 0.4-V, 0.138-fJ/Cycle Single-Phase-Clocking Redundant-Transition-Free 24T Flip-Flop With Change-Sensing Scheme in 40-nm CMOS

IEEE journal of solid-state circuits, 2018-10, Vol.53 (10), p.2806-2817

2018

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A 0.4 V 12T 2RW dual-port SRAM with suppressed common-row-access disturbance

Microelectronics, 2017-11, Vol.69, p.78-85

2017

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A 0.4V 12T 2RW dual-port SRAM with suppressed common-row-access disturbance

Microelectronics, 2017-11, Vol.69, p.78-85

2017

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A 0.5 V 8-12 Bit 300 KSPS SAR ADC With Adaptive Conversion Time Detection-and-Control for High Immunity to PVT Variations

IEEE access, 2020, Vol.8, p.101359-101368

2020

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A 0.506-pJ 16-kb 8T SRAM With Vertical Read Wordlines and Selective Dual Split Power Lines

IEEE transactions on very large scale integration (VLSI) systems, 2020-06, Vol.28 (6), p.1345-1356

2020

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A 0.5V 29pJ/cycle sensor node processor for intelligent sensing applications

2014 International SoC Design Conference (ISOCC), 2014, p.70-71

2014

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A 0.6-to-1.2 V Scaling-Friendly Discrete-Time OTA-Free Linear VCO-Based TEXPRESERVE0 ADC Suitable for DVFS

IEEE transactions on circuits and systems. I, Regular papers, 2024-04, p.1-14

2024

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A 0.6-to-1.2 V Scaling-Friendly Discrete-Time OTA-Free Linear VCO-Based ΔΣ ADC Suitable for DVFS

IEEE transactions on circuits and systems. I, Regular papers, 2024-04, Vol.71 (4), p.1481-1494

2024

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A 0.6-to-1.2 V Scaling Friendly Discrete-Time OTA-Free ΔΣ-ADC for IoT Applications

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021, p.219-222

2021

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0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance

IEEE journal of solid-state circuits, 2014-07, Vol.49 (7), p.1487-1498

2014

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A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019, p.345-348

2019

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A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks

IEEE transactions on circuits and systems. I, Regular papers, 2023-04, Vol.70 (4), p.1-11

2023

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A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM

IEEE journal of solid-state circuits, 2003-11, Vol.38 (11), p.1943-1951

2003

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A 1.2 V 1.5 Gb/s 72 Mb DDR3 SRAM

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC, 2003, p.300-494 vol.1

2003

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A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.1847-1850 Vol. 2

2005

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1/8 척도 CANDU6 감속재 순환 유동 실험에 대한 PIV 속도장 측정

한국가시화정보학회지, 2014, Vol.12 (1), p.18-24

2014

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A 1-Mb RRAM Macro With 9.8 ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation

IEEE transactions on circuits and systems. II, Express briefs, 2024-05, Vol.71 (5), p.2564-2568

2024

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A 10-bit, 40 Msamples/s cascading folding and interpolating A/D converter with wide range error correction

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434), 2000, p.57-60

2000

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1189 HISTOPATHOLOGIC EVALUATION OF NON-NEOPLASTIC RENAL PARENCHYME ADJACENT TO TUMOR IN PARTIAL NEPHRECTOMY SPECIMENS FOR RENAL CELL CARCINOMA

The Journal of urology, 2013-04, Vol.189 (4), p.e486-e486

2013

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A 12-bit Multi-Channel R-R DAC Using a Shared Resistor String Scheme for Area-Efficient Display Source Driver

IEEE transactions on circuits and systems. I, Regular papers, 2018-11, Vol.65 (11), p.3688-3697

2018

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A 0.007 mm 2 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS

A 0.007 mm2 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS

A 0.016 mV/mA Cross-Regulation 5-Output SIMO DC-DC Buck Converter Using Output-Voltage-Aware Charge Control Scheme

A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing

0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization

A 0.4-V, 0.138-fJ/Cycle Single-Phase-Clocking Redundant-Transition-Free 24T Flip-Flop With Change-Sensing Scheme in 40-nm CMOS

A 0.4 V 12T 2RW dual-port SRAM with suppressed common-row-access disturbance

A 0.4V 12T 2RW dual-port SRAM with suppressed common-row-access disturbance

A 0.5 V 8-12 Bit 300 KSPS SAR ADC With Adaptive Conversion Time Detection-and-Control for High Immunity to PVT Variations

A 0.506-pJ 16-kb 8T SRAM With Vertical Read Wordlines and Selective Dual Split Power Lines

A 0.5V 29pJ/cycle sensor node processor for intelligent sensing applications

A 0.6-to-1.2 V Scaling-Friendly Discrete-Time OTA-Free Linear VCO-Based TEXPRESERVE0 ADC Suitable for DVFS

A 0.6-to-1.2 V Scaling-Friendly Discrete-Time OTA-Free Linear VCO-Based ΔΣ ADC Suitable for DVFS

A 0.6-to-1.2 V Scaling Friendly Discrete-Time OTA-Free ΔΣ-ADC for IoT Applications

0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance

A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation

A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks

A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM

A 1.2 V 1.5 Gb/s 72 Mb DDR3 SRAM

A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch

1/8 척도 CANDU6 감속재 순환 유동 실험에 대한 PIV 속도장 측정

A 1-Mb RRAM Macro With 9.8 ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation

A 10-bit, 40 Msamples/s cascading folding and interpolating A/D converter with wide range error correction

1189 HISTOPATHOLOGIC EVALUATION OF NON-NEOPLASTIC RENAL PARENCHYME ADJACENT TO TUMOR IN PARTIAL NEPHRECTOMY SPECIMENS FOR RENAL CELL CARCINOMA

A 12-bit Multi-Channel R-R DAC Using a Shared Resistor String Scheme for Area-Efficient Display Source Driver

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